\doxysection{core\+\_\+cm7.\+h}
\hypertarget{core__cm7_8h_source}{}\label{core__cm7_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_cm7.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_cm7.h}}
\mbox{\hyperlink{core__cm7_8h}{Go to the documentation of this file.}}
\begin{DoxyCode}{0}
\DoxyCodeLine{00001\ \textcolor{comment}{/**************************************************************************/}}
\DoxyCodeLine{00007\ \textcolor{comment}{/*}}
\DoxyCodeLine{00008\ \textcolor{comment}{\ *\ Copyright\ (c)\ 2009-\/2019\ Arm\ Limited.\ All\ rights\ reserved.}}
\DoxyCodeLine{00009\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00010\ \textcolor{comment}{\ *\ SPDX-\/License-\/Identifier:\ Apache-\/2.0}}
\DoxyCodeLine{00011\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00012\ \textcolor{comment}{\ *\ Licensed\ under\ the\ Apache\ License,\ Version\ 2.0\ (the\ License);\ you\ may}}
\DoxyCodeLine{00013\ \textcolor{comment}{\ *\ not\ use\ this\ file\ except\ in\ compliance\ with\ the\ License.}}
\DoxyCodeLine{00014\ \textcolor{comment}{\ *\ You\ may\ obtain\ a\ copy\ of\ the\ License\ at}}
\DoxyCodeLine{00015\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00016\ \textcolor{comment}{\ *\ www.apache.org/licenses/LICENSE-\/2.0}}
\DoxyCodeLine{00017\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00018\ \textcolor{comment}{\ *\ Unless\ required\ by\ applicable\ law\ or\ agreed\ to\ in\ writing,\ software}}
\DoxyCodeLine{00019\ \textcolor{comment}{\ *\ distributed\ under\ the\ License\ is\ distributed\ on\ an\ AS\ IS\ BASIS,\ WITHOUT}}
\DoxyCodeLine{00020\ \textcolor{comment}{\ *\ WARRANTIES\ OR\ CONDITIONS\ OF\ ANY\ KIND,\ either\ express\ or\ implied.}}
\DoxyCodeLine{00021\ \textcolor{comment}{\ *\ See\ the\ License\ for\ the\ specific\ language\ governing\ permissions\ and}}
\DoxyCodeLine{00022\ \textcolor{comment}{\ *\ limitations\ under\ the\ License.}}
\DoxyCodeLine{00023\ \textcolor{comment}{\ */}}
\DoxyCodeLine{00024\ }
\DoxyCodeLine{00025\ \textcolor{preprocessor}{\#if\ \ \ defined\ (\ \_\_ICCARM\_\_\ )}}
\DoxyCodeLine{00026\ \textcolor{preprocessor}{\ \ \#pragma\ system\_include\ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ treat\ file\ as\ system\ include\ file\ for\ MISRA\ check\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00027\ \textcolor{preprocessor}{\#elif\ defined\ (\_\_clang\_\_)}}
\DoxyCodeLine{00028\ \textcolor{preprocessor}{\ \ \#pragma\ clang\ system\_header\ \ \ }\textcolor{comment}{/*\ treat\ file\ as\ system\ include\ file\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00029\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00030\ }
\DoxyCodeLine{00031\ \textcolor{preprocessor}{\#ifndef\ \_\_CORE\_CM7\_H\_GENERIC}}
\DoxyCodeLine{00032\ \textcolor{preprocessor}{\#define\ \_\_CORE\_CM7\_H\_GENERIC}}
\DoxyCodeLine{00033\ }
\DoxyCodeLine{00034\ \textcolor{preprocessor}{\#include\ <stdint.h>}}
\DoxyCodeLine{00035\ }
\DoxyCodeLine{00036\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00037\ \ \textcolor{keyword}{extern}\ \textcolor{stringliteral}{"{}C"{}}\ \{}
\DoxyCodeLine{00038\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00039\ }
\DoxyCodeLine{00053\ }
\DoxyCodeLine{00054\ }
\DoxyCodeLine{00055\ \textcolor{comment}{/*******************************************************************************}}
\DoxyCodeLine{00056\ \textcolor{comment}{\ *\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CMSIS\ definitions}}
\DoxyCodeLine{00057\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{00062\ }
\DoxyCodeLine{00063\ \textcolor{preprocessor}{\#include\ "{}\mbox{\hyperlink{cmsis__version_8h}{cmsis\_version.h}}"{}}}
\DoxyCodeLine{00064\ }
\DoxyCodeLine{00065\ \textcolor{comment}{/*\ CMSIS\ CM7\ definitions\ */}}
\DoxyCodeLine{00066\ \textcolor{preprocessor}{\#define\ \_\_CM7\_CMSIS\_VERSION\_MAIN\ \ (\_\_CM\_CMSIS\_VERSION\_MAIN)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00067\ \textcolor{preprocessor}{\#define\ \_\_CM7\_CMSIS\_VERSION\_SUB\ \ \ (\ \_\_CM\_CMSIS\_VERSION\_SUB)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00068\ \textcolor{preprocessor}{\#define\ \_\_CM7\_CMSIS\_VERSION\ \ \ \ \ \ \ ((\_\_CM7\_CMSIS\_VERSION\_MAIN\ <<\ 16U)\ |\ \(\backslash\)}}
\DoxyCodeLine{00069\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_CM7\_CMSIS\_VERSION\_SUB\ \ \ \ \ \ \ \ \ \ \ )\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00070\ }
\DoxyCodeLine{00071\ \textcolor{preprocessor}{\#define\ \_\_CORTEX\_M\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00072\ }
\DoxyCodeLine{00076\ \textcolor{preprocessor}{\#if\ defined\ (\ \_\_CC\_ARM\ )}}
\DoxyCodeLine{00077\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_TARGET\_FPU\_VFP}}
\DoxyCodeLine{00078\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00079\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00080\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00081\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00082\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00083\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00084\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00085\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00086\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00087\ }
\DoxyCodeLine{00088\ \textcolor{preprocessor}{\#elif\ defined\ (\_\_ARMCC\_VERSION)\ \&\&\ (\_\_ARMCC\_VERSION\ >=\ 6010050)}}
\DoxyCodeLine{00089\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_ARM\_FP}}
\DoxyCodeLine{00090\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00091\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00092\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00093\ \textcolor{preprocessor}{\ \ \ \ \ \ \#warning\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00094\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00095\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00096\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00097\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00098\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00099\ }
\DoxyCodeLine{00100\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_GNUC\_\_\ )}}
\DoxyCodeLine{00101\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_VFP\_FP\_\_)\ \&\&\ !defined(\_\_SOFTFP\_\_)}}
\DoxyCodeLine{00102\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00103\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00104\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00105\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00106\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00107\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00108\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00109\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00110\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00111\ }
\DoxyCodeLine{00112\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_ICCARM\_\_\ )}}
\DoxyCodeLine{00113\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_ARMVFP\_\_}}
\DoxyCodeLine{00114\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00115\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00116\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00117\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00118\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00119\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00120\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00121\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00122\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00123\ }
\DoxyCodeLine{00124\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_TI\_ARM\_\_\ )}}
\DoxyCodeLine{00125\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_TI\_VFP\_SUPPORT\_\_}}
\DoxyCodeLine{00126\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00127\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00128\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00129\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00130\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00131\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00132\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00133\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00134\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00135\ }
\DoxyCodeLine{00136\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_TASKING\_\_\ )}}
\DoxyCodeLine{00137\ \textcolor{preprocessor}{\ \ \#if\ defined\ \_\_FPU\_VFP\_\_}}
\DoxyCodeLine{00138\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00139\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00140\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00141\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00142\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00143\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00144\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00145\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00146\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00147\ }
\DoxyCodeLine{00148\ \textcolor{preprocessor}{\#elif\ defined\ (\ \_\_CSMC\_\_\ )}}
\DoxyCodeLine{00149\ \textcolor{preprocessor}{\ \ \#if\ (\ \_\_CSMC\_\_\ \&\ 0x400U)}}
\DoxyCodeLine{00150\ \textcolor{preprocessor}{\ \ \ \ \#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{00151\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 1U}}
\DoxyCodeLine{00152\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{00153\ \textcolor{preprocessor}{\ \ \ \ \ \ \#error\ "{}Compiler\ generates\ FPU\ instructions\ for\ a\ device\ without\ an\ FPU\ (check\ \_\_FPU\_PRESENT)"{}}}
\DoxyCodeLine{00154\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00155\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{00156\ \textcolor{preprocessor}{\ \ \#else}}
\DoxyCodeLine{00157\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_USED\ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00158\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00159\ }
\DoxyCodeLine{00160\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00161\ }
\DoxyCodeLine{00162\ \textcolor{preprocessor}{\#include\ "{}\mbox{\hyperlink{cmsis__compiler_8h}{cmsis\_compiler.h}}"{}}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ CMSIS\ compiler\ specific\ defines\ */}}
\DoxyCodeLine{00163\ }
\DoxyCodeLine{00164\ }
\DoxyCodeLine{00165\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00166\ \}}
\DoxyCodeLine{00167\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00168\ }
\DoxyCodeLine{00169\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_CORE\_CM7\_H\_GENERIC\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00170\ }
\DoxyCodeLine{00171\ \textcolor{preprocessor}{\#ifndef\ \_\_CMSIS\_GENERIC}}
\DoxyCodeLine{00172\ }
\DoxyCodeLine{00173\ \textcolor{preprocessor}{\#ifndef\ \_\_CORE\_CM7\_H\_DEPENDANT}}
\DoxyCodeLine{00174\ \textcolor{preprocessor}{\#define\ \_\_CORE\_CM7\_H\_DEPENDANT}}
\DoxyCodeLine{00175\ }
\DoxyCodeLine{00176\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00177\ \ \textcolor{keyword}{extern}\ \textcolor{stringliteral}{"{}C"{}}\ \{}
\DoxyCodeLine{00178\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00179\ }
\DoxyCodeLine{00180\ \textcolor{comment}{/*\ check\ device\ defines\ and\ use\ defaults\ */}}
\DoxyCodeLine{00181\ \textcolor{preprocessor}{\#if\ defined\ \_\_CHECK\_DEVICE\_DEFINES}}
\DoxyCodeLine{00182\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_CM7\_REV}}
\DoxyCodeLine{00183\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_CM7\_REV\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x0000U}}
\DoxyCodeLine{00184\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_CM7\_REV\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00185\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00186\ }
\DoxyCodeLine{00187\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_FPU\_PRESENT}}
\DoxyCodeLine{00188\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_FPU\_PRESENT\ \ \ \ \ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00189\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_FPU\_PRESENT\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00190\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00191\ }
\DoxyCodeLine{00192\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_MPU\_PRESENT}}
\DoxyCodeLine{00193\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_MPU\_PRESENT\ \ \ \ \ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00194\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_MPU\_PRESENT\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00195\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00196\ }
\DoxyCodeLine{00197\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_ICACHE\_PRESENT}}
\DoxyCodeLine{00198\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_ICACHE\_PRESENT\ \ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00199\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_ICACHE\_PRESENT\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00200\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00201\ }
\DoxyCodeLine{00202\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_DCACHE\_PRESENT}}
\DoxyCodeLine{00203\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_DCACHE\_PRESENT\ \ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00204\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_DCACHE\_PRESENT\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00205\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00206\ }
\DoxyCodeLine{00207\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_DTCM\_PRESENT}}
\DoxyCodeLine{00208\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_DTCM\_PRESENT\ \ \ \ \ \ \ \ \ \ \ \ 0U}}
\DoxyCodeLine{00209\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_DTCM\_PRESENT\ \ \ \ \ \ \ \ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00210\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00211\ }
\DoxyCodeLine{00212\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_NVIC\_PRIO\_BITS}}
\DoxyCodeLine{00213\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_NVIC\_PRIO\_BITS\ \ \ \ \ \ \ \ \ \ 3U}}
\DoxyCodeLine{00214\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_NVIC\_PRIO\_BITS\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00215\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00216\ }
\DoxyCodeLine{00217\ \textcolor{preprocessor}{\ \ \#ifndef\ \_\_Vendor\_SysTickConfig}}
\DoxyCodeLine{00218\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_\_Vendor\_SysTickConfig\ \ \ \ 0U}}
\DoxyCodeLine{00219\ \textcolor{preprocessor}{\ \ \ \ \#warning\ "{}\_\_Vendor\_SysTickConfig\ not\ defined\ in\ device\ header\ file;\ using\ default!"{}}}
\DoxyCodeLine{00220\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{00221\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00222\ }
\DoxyCodeLine{00223\ \textcolor{comment}{/*\ IO\ definitions\ (access\ restrictions\ to\ peripheral\ registers)\ */}}
\DoxyCodeLine{00231\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00232\ \textcolor{preprocessor}{\ \ \#define\ \ \ \_\_I\ \ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00233\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{00234\ \textcolor{preprocessor}{\ \ \#define\ \ \ \_\_I\ \ \ \ \ volatile\ const\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00235\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00236\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_O\ \ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00237\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_IO\ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00238\ }
\DoxyCodeLine{00239\ \textcolor{comment}{/*\ following\ defines\ should\ be\ used\ for\ structure\ members\ */}}
\DoxyCodeLine{00240\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_IM\ \ \ \ \ volatile\ const\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00241\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_OM\ \ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00242\ \textcolor{preprocessor}{\#define\ \ \ \ \ \_\_IOM\ \ \ \ volatile\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00243\ }
\DoxyCodeLine{00245\ }
\DoxyCodeLine{00246\ }
\DoxyCodeLine{00247\ }
\DoxyCodeLine{00248\ \textcolor{comment}{/*******************************************************************************}}
\DoxyCodeLine{00249\ \textcolor{comment}{\ *\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Register\ Abstraction}}
\DoxyCodeLine{00250\ \textcolor{comment}{\ \ Core\ Register\ contain:}}
\DoxyCodeLine{00251\ \textcolor{comment}{\ \ -\/\ Core\ Register}}
\DoxyCodeLine{00252\ \textcolor{comment}{\ \ -\/\ Core\ NVIC\ Register}}
\DoxyCodeLine{00253\ \textcolor{comment}{\ \ -\/\ Core\ SCB\ Register}}
\DoxyCodeLine{00254\ \textcolor{comment}{\ \ -\/\ Core\ SysTick\ Register}}
\DoxyCodeLine{00255\ \textcolor{comment}{\ \ -\/\ Core\ Debug\ Register}}
\DoxyCodeLine{00256\ \textcolor{comment}{\ \ -\/\ Core\ MPU\ Register}}
\DoxyCodeLine{00257\ \textcolor{comment}{\ \ -\/\ Core\ FPU\ Register}}
\DoxyCodeLine{00258\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{00263\ }
\DoxyCodeLine{00270\ }
\DoxyCodeLine{00274\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{union}}
\DoxyCodeLine{00275\ \{}
\DoxyCodeLine{00276\ \ \ \textcolor{keyword}{struct}}
\DoxyCodeLine{00277\ \ \ \{}
\DoxyCodeLine{00278\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gadc48ab5246cb746cfc6b8e9dfbae18db}{\_reserved0}}:16;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00279\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga9c12baa27385fc2761239fae065a797e}{GE}}:4;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00280\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac4f7c02b560bd70ef59ee9d7f05d8f37}{\_reserved1}}:7;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00281\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac66d3c647e4c23f4188452c37ef37506}{Q}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00282\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga22c2ba433e5853c5a35a25cd28aa4d73}{V}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00283\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga47ae505ee5e1cd36c89db762409d06ef}{C}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00284\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad85c5115bc4444218571a686a1567397}{Z}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00285\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2cb874423f2ad12a3e46fe85e6834632}{N}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00286\ \ \ \}\ b;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00287\ \ \ uint32\_t\ w;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00288\ \}\ \mbox{\hyperlink{union_a_p_s_r___type}{APSR\_Type}};}
\DoxyCodeLine{00289\ }
\DoxyCodeLine{00290\ \textcolor{comment}{/*\ APSR\ Register\ Definitions\ */}}
\DoxyCodeLine{00291\ \textcolor{preprocessor}{\#define\ APSR\_N\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00292\ \textcolor{preprocessor}{\#define\ APSR\_N\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_N\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00293\ }
\DoxyCodeLine{00294\ \textcolor{preprocessor}{\#define\ APSR\_Z\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00295\ \textcolor{preprocessor}{\#define\ APSR\_Z\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_Z\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00296\ }
\DoxyCodeLine{00297\ \textcolor{preprocessor}{\#define\ APSR\_C\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00298\ \textcolor{preprocessor}{\#define\ APSR\_C\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_C\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00299\ }
\DoxyCodeLine{00300\ \textcolor{preprocessor}{\#define\ APSR\_V\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00301\ \textcolor{preprocessor}{\#define\ APSR\_V\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_V\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00302\ }
\DoxyCodeLine{00303\ \textcolor{preprocessor}{\#define\ APSR\_Q\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00304\ \textcolor{preprocessor}{\#define\ APSR\_Q\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ APSR\_Q\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00305\ }
\DoxyCodeLine{00306\ \textcolor{preprocessor}{\#define\ APSR\_GE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00307\ \textcolor{preprocessor}{\#define\ APSR\_GE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ APSR\_GE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00308\ }
\DoxyCodeLine{00309\ }
\DoxyCodeLine{00313\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{union}}
\DoxyCodeLine{00314\ \{}
\DoxyCodeLine{00315\ \ \ \textcolor{keyword}{struct}}
\DoxyCodeLine{00316\ \ \ \{}
\DoxyCodeLine{00317\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaca9412bfc89bcb1dd79fb71921b44c05}{ISR}}:9;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00318\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga49d4c2d54e927d4e20c151ee24f9d943}{\_reserved0}}:23;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00319\ \ \ \}\ b;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00320\ \ \ uint32\_t\ w;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00321\ \}\ \mbox{\hyperlink{union_i_p_s_r___type}{IPSR\_Type}};}
\DoxyCodeLine{00322\ }
\DoxyCodeLine{00323\ \textcolor{comment}{/*\ IPSR\ Register\ Definitions\ */}}
\DoxyCodeLine{00324\ \textcolor{preprocessor}{\#define\ IPSR\_ISR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00325\ \textcolor{preprocessor}{\#define\ IPSR\_ISR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ IPSR\_ISR\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00326\ }
\DoxyCodeLine{00327\ }
\DoxyCodeLine{00331\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{union}}
\DoxyCodeLine{00332\ \{}
\DoxyCodeLine{00333\ \ \ \textcolor{keyword}{struct}}
\DoxyCodeLine{00334\ \ \ \{}
\DoxyCodeLine{00335\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga90088752a29ec30050bb42ba57329252}{ISR}}:9;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00336\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad777beab09ddb57aea480aad1fadb900}{\_reserved0}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00337\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gadf9a973ed27b386c847b9cac059a53ce}{ICI\_IT\_1}}:6;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00338\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad664f02372bf37a9bbc0f0d8626f21a8}{GE}}:4;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00339\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad49340b802ebec07f850d4210f24849b}{\_reserved1}}:4;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00340\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga16780d100cce117f48f6e939de59b597}{T}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00341\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac517baafad48f4e5d4986d4b6e7d5197}{ICI\_IT\_2}}:2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00342\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4bad87158db19ffdd5183e4c94fdc125}{Q}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00343\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga235bb11aafe71623a97b357261a25c35}{V}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00344\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga333cdc474749744675134f9f6d25de01}{C}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00345\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga3a4a99366939c29a615a1f092ae7f281}{Z}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00346\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab0035b1df04f9adb4c26bb1a80ce89af}{N}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00347\ \ \ \}\ b;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00348\ \ \ uint32\_t\ w;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00349\ \}\ \mbox{\hyperlink{unionx_p_s_r___type}{xPSR\_Type}};}
\DoxyCodeLine{00350\ }
\DoxyCodeLine{00351\ \textcolor{comment}{/*\ xPSR\ Register\ Definitions\ */}}
\DoxyCodeLine{00352\ \textcolor{preprocessor}{\#define\ xPSR\_N\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00353\ \textcolor{preprocessor}{\#define\ xPSR\_N\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_N\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00354\ }
\DoxyCodeLine{00355\ \textcolor{preprocessor}{\#define\ xPSR\_Z\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00356\ \textcolor{preprocessor}{\#define\ xPSR\_Z\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_Z\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00357\ }
\DoxyCodeLine{00358\ \textcolor{preprocessor}{\#define\ xPSR\_C\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00359\ \textcolor{preprocessor}{\#define\ xPSR\_C\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_C\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00360\ }
\DoxyCodeLine{00361\ \textcolor{preprocessor}{\#define\ xPSR\_V\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00362\ \textcolor{preprocessor}{\#define\ xPSR\_V\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_V\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00363\ }
\DoxyCodeLine{00364\ \textcolor{preprocessor}{\#define\ xPSR\_Q\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00365\ \textcolor{preprocessor}{\#define\ xPSR\_Q\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_Q\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00366\ }
\DoxyCodeLine{00367\ \textcolor{preprocessor}{\#define\ xPSR\_ICI\_IT\_2\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00368\ \textcolor{preprocessor}{\#define\ xPSR\_ICI\_IT\_2\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ xPSR\_ICI\_IT\_2\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00369\ }
\DoxyCodeLine{00370\ \textcolor{preprocessor}{\#define\ xPSR\_T\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00371\ \textcolor{preprocessor}{\#define\ xPSR\_T\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ xPSR\_T\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00372\ }
\DoxyCodeLine{00373\ \textcolor{preprocessor}{\#define\ xPSR\_GE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00374\ \textcolor{preprocessor}{\#define\ xPSR\_GE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ xPSR\_GE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00375\ }
\DoxyCodeLine{00376\ \textcolor{preprocessor}{\#define\ xPSR\_ICI\_IT\_1\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00377\ \textcolor{preprocessor}{\#define\ xPSR\_ICI\_IT\_1\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3FUL\ <<\ xPSR\_ICI\_IT\_1\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00378\ }
\DoxyCodeLine{00379\ \textcolor{preprocessor}{\#define\ xPSR\_ISR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00380\ \textcolor{preprocessor}{\#define\ xPSR\_ISR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ xPSR\_ISR\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00381\ }
\DoxyCodeLine{00382\ }
\DoxyCodeLine{00386\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{union}}
\DoxyCodeLine{00387\ \{}
\DoxyCodeLine{00388\ \ \ \textcolor{keyword}{struct}}
\DoxyCodeLine{00389\ \ \ \{}
\DoxyCodeLine{00390\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga720c80f45c6eed9fc7cbbee941b7918b}{nPRIV}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00391\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2d2df497626342a90e7da011baf1fe71}{SPSEL}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00392\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab04e8e38a8fff4db9026482a5a5ee237}{FPCA}}:1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00393\ \ \ \ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac540491b4df0acbfaa565f63677ca4d0}{\_reserved0}}:29;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00394\ \ \ \}\ b;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00395\ \ \ uint32\_t\ w;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00396\ \}\ \mbox{\hyperlink{union_c_o_n_t_r_o_l___type}{CONTROL\_Type}};}
\DoxyCodeLine{00397\ }
\DoxyCodeLine{00398\ \textcolor{comment}{/*\ CONTROL\ Register\ Definitions\ */}}
\DoxyCodeLine{00399\ \textcolor{preprocessor}{\#define\ CONTROL\_FPCA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00400\ \textcolor{preprocessor}{\#define\ CONTROL\_FPCA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ CONTROL\_FPCA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00401\ }
\DoxyCodeLine{00402\ \textcolor{preprocessor}{\#define\ CONTROL\_SPSEL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00403\ \textcolor{preprocessor}{\#define\ CONTROL\_SPSEL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ CONTROL\_SPSEL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00404\ }
\DoxyCodeLine{00405\ \textcolor{preprocessor}{\#define\ CONTROL\_nPRIV\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00406\ \textcolor{preprocessor}{\#define\ CONTROL\_nPRIV\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ CONTROL\_nPRIV\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00407\ }
\DoxyCodeLine{00409\ }
\DoxyCodeLine{00410\ }
\DoxyCodeLine{00417\ }
\DoxyCodeLine{00421\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{00422\ \{}
\DoxyCodeLine{00423\ \ \ \_\_IOM\ uint32\_t\ ISER[8U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00424\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[24U];}
\DoxyCodeLine{00425\ \ \ \_\_IOM\ uint32\_t\ ICER[8U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00426\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[24U];}
\DoxyCodeLine{00427\ \ \ \_\_IOM\ uint32\_t\ ISPR[8U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00428\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[24U];}
\DoxyCodeLine{00429\ \ \ \_\_IOM\ uint32\_t\ ICPR[8U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00430\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[24U];}
\DoxyCodeLine{00431\ \ \ \_\_IOM\ uint32\_t\ IABR[8U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00432\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[56U];}
\DoxyCodeLine{00433\ \ \ \_\_IOM\ uint8\_t\ \ IP[240U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00434\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[644U];}
\DoxyCodeLine{00435\ \ \ \_\_OM\ \ uint32\_t\ STIR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00436\ \}\ \ \mbox{\hyperlink{struct_n_v_i_c___type}{NVIC\_Type}};}
\DoxyCodeLine{00437\ }
\DoxyCodeLine{00438\ \textcolor{comment}{/*\ Software\ Triggered\ Interrupt\ Register\ Definitions\ */}}
\DoxyCodeLine{00439\ \textcolor{preprocessor}{\#define\ NVIC\_STIR\_INTID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00440\ \textcolor{preprocessor}{\#define\ NVIC\_STIR\_INTID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ NVIC\_STIR\_INTID\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00441\ }
\DoxyCodeLine{00443\ }
\DoxyCodeLine{00444\ }
\DoxyCodeLine{00451\ }
\DoxyCodeLine{00455\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{00456\ \{}
\DoxyCodeLine{00457\ \ \ \_\_IM\ \ uint32\_t\ CPUID;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00458\ \ \ \_\_IOM\ uint32\_t\ ICSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00459\ \ \ \_\_IOM\ uint32\_t\ VTOR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00460\ \ \ \_\_IOM\ uint32\_t\ AIRCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00461\ \ \ \_\_IOM\ uint32\_t\ SCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00462\ \ \ \_\_IOM\ uint32\_t\ CCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00463\ \ \ \_\_IOM\ uint8\_t\ \ SHPR[12U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00464\ \ \ \_\_IOM\ uint32\_t\ SHCSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00465\ \ \ \_\_IOM\ uint32\_t\ CFSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00466\ \ \ \_\_IOM\ uint32\_t\ HFSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00467\ \ \ \_\_IOM\ uint32\_t\ DFSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00468\ \ \ \_\_IOM\ uint32\_t\ MMFAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00469\ \ \ \_\_IOM\ uint32\_t\ BFAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00470\ \ \ \_\_IOM\ uint32\_t\ AFSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00471\ \ \ \_\_IM\ \ uint32\_t\ ID\_PFR[2U];\ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00472\ \ \ \_\_IM\ \ uint32\_t\ ID\_DFR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00473\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga9c9a1d805f8e99b9fd3ab4f455b6333a}{ID\_AFR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00474\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga781ef24d88610a432e7d5b179d78de47}{ID\_MFR}}[4U];\ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00475\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga5be03d185d9bde32c5b9028f792f8e1e}{ID\_ISAR}}[5U];\ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00476\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1U];}
\DoxyCodeLine{00477\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad9899f5775251cf5ef0cb0845527afc2}{CLIDR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00478\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf3fe705fef8762763b6d61dbdf0ccc3d}{CTR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00479\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gafd063c9297a1a3b67e6d1d5e179e6a0e}{CCSIDR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00480\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad3884e8b6504ec63c1eaa8742e94df3d}{CSSELR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00481\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac6a860c1b8d8154a1f00d99d23b67764}{CPACR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00482\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[93U];}
\DoxyCodeLine{00483\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gad70825dd0869b7ccd07fb2b8680fcdb6}{STIR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00484\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[15U];}
\DoxyCodeLine{00485\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga7a1ba0f875c0e97c1673882b1106e66b}{MVFR0}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00486\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga75d6299150fdcbbcb765e22ff27c432e}{MVFR1}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00487\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga280ef961518ecee3ed43a86404853c3d}{MVFR2}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00488\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[1U];}
\DoxyCodeLine{00489\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga573260e7836dbc43707df97dd475a0c8}{ICIALLU}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00490\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED6[1U];}
\DoxyCodeLine{00491\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga5eca5a3e5aedd89a9655df8f5798e2b0}{ICIMVAU}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00492\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4be79491ab1ed14f3b0237ba7e69063c}{DCIMVAC}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00493\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga22bcfd7e1bffebdbe98cdbc8d77a2f42}{DCISW}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00494\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaae3caeea159ab54859ea11397f942cfa}{DCCMVAU}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00495\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga042e3622c98de4e908cfda4f70d1f097}{DCCMVAC}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00496\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gab95cc818be9fa7d25ae516f3fe6b7788}{DCCSW}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00497\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4f59813582b53feb5f1afbbad3db2022}{DCCIMVAC}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00498\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf50f7a0a9574fe0e24a68bb4eca75140}{DCCISW}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00499\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED7[6U];}
\DoxyCodeLine{00500\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaba8abbd3db06a07b50f56547501983f9}{ITCMCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00501\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga2836e932734240076ce91cf4484cdf43}{DTCMCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00502\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga0d53bcea294422b5b4ecfdcd9cdc1773}{AHBPCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00503\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga51f9bd107a4e1d46ba647384e5c825b5}{CACR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00504\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga8c9d9eac30594dd061d34cfaacd5e4bb}{AHBSCR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00505\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED8[1U];}
\DoxyCodeLine{00506\ \ \ \_\_IOM\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga35a95c9a21f43a569a7ac212acb4cee7}{ABFSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00507\ \}\ \mbox{\hyperlink{struct_s_c_b___type}{SCB\_Type}};}
\DoxyCodeLine{00508\ }
\DoxyCodeLine{00509\ \textcolor{comment}{/*\ SCB\ CPUID\ Register\ Definitions\ */}}
\DoxyCodeLine{00510\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_IMPLEMENTER\_Pos\ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00511\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_IMPLEMENTER\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ SCB\_CPUID\_IMPLEMENTER\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00512\ }
\DoxyCodeLine{00513\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_VARIANT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00514\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_VARIANT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CPUID\_VARIANT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00515\ }
\DoxyCodeLine{00516\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_ARCHITECTURE\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00517\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_ARCHITECTURE\_Msk\ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CPUID\_ARCHITECTURE\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00518\ }
\DoxyCodeLine{00519\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_PARTNO\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00520\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_PARTNO\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFUL\ <<\ SCB\_CPUID\_PARTNO\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00521\ }
\DoxyCodeLine{00522\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_REVISION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00523\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_REVISION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ SCB\_CPUID\_REVISION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00524\ }
\DoxyCodeLine{00525\ \textcolor{comment}{/*\ SCB\ Interrupt\ Control\ State\ Register\ Definitions\ */}}
\DoxyCodeLine{00526\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_NMIPENDSET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00527\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_NMIPENDSET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_NMIPENDSET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00528\ }
\DoxyCodeLine{00529\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVSET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00530\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVSET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSVSET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00531\ }
\DoxyCodeLine{00532\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVCLR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00533\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSVCLR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSVCLR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00534\ }
\DoxyCodeLine{00535\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTSET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00536\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTSET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSTSET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00537\ }
\DoxyCodeLine{00538\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTCLR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00539\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDSTCLR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDSTCLR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00540\ }
\DoxyCodeLine{00541\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPREEMPT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 23U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00542\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPREEMPT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_ISRPREEMPT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00543\ }
\DoxyCodeLine{00544\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPENDING\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00545\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_ISRPENDING\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_ISRPENDING\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00546\ }
\DoxyCodeLine{00547\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTPENDING\_Pos\ \ \ \ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00548\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTPENDING\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_ICSR\_VECTPENDING\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00549\ }
\DoxyCodeLine{00550\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_RETTOBASE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00551\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_RETTOBASE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_RETTOBASE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00552\ }
\DoxyCodeLine{00553\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTACTIVE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00554\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_VECTACTIVE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ SCB\_ICSR\_VECTACTIVE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00555\ }
\DoxyCodeLine{00556\ \textcolor{comment}{/*\ SCB\ Vector\ Table\ Offset\ Register\ Definitions\ */}}
\DoxyCodeLine{00557\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00558\ \textcolor{preprocessor}{\#define\ SCB\_VTOR\_TBLOFF\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFFFFUL\ <<\ SCB\_VTOR\_TBLOFF\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00559\ }
\DoxyCodeLine{00560\ \textcolor{comment}{/*\ SCB\ Application\ Interrupt\ and\ Reset\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00561\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00562\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_AIRCR\_VECTKEY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00563\ }
\DoxyCodeLine{00564\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEYSTAT\_Pos\ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00565\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEYSTAT\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_AIRCR\_VECTKEYSTAT\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00566\ }
\DoxyCodeLine{00567\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_ENDIANESS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 15U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00568\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_ENDIANESS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_ENDIANESS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00569\ }
\DoxyCodeLine{00570\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00571\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_AIRCR\_PRIGROUP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00572\ }
\DoxyCodeLine{00573\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Pos\ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00574\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_SYSRESETREQ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00575\ }
\DoxyCodeLine{00576\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTCLRACTIVE\_Pos\ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00577\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTCLRACTIVE\_Msk\ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_VECTCLRACTIVE\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00578\ }
\DoxyCodeLine{00579\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTRESET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00580\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTRESET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_AIRCR\_VECTRESET\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00581\ }
\DoxyCodeLine{00582\ \textcolor{comment}{/*\ SCB\ System\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00583\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SEVONPEND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00584\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SEVONPEND\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SEVONPEND\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00585\ }
\DoxyCodeLine{00586\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00587\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPDEEP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00588\ }
\DoxyCodeLine{00589\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPONEXIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00590\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPONEXIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPONEXIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00591\ }
\DoxyCodeLine{00592\ \textcolor{comment}{/*\ SCB\ Configuration\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00593\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00594\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_BP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00595\ }
\DoxyCodeLine{00596\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_IC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00597\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_IC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_IC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00598\ }
\DoxyCodeLine{00599\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00600\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_DC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00601\ }
\DoxyCodeLine{00602\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_STKALIGN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00603\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_STKALIGN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_STKALIGN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00604\ }
\DoxyCodeLine{00605\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00606\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_BFHFNMIGN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00607\ }
\DoxyCodeLine{00608\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DIV\_0\_TRP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00609\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DIV\_0\_TRP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_DIV\_0\_TRP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00610\ }
\DoxyCodeLine{00611\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_UNALIGN\_TRP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00612\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_UNALIGN\_TRP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_UNALIGN\_TRP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00613\ }
\DoxyCodeLine{00614\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_USERSETMPEND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00615\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_USERSETMPEND\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_USERSETMPEND\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00616\ }
\DoxyCodeLine{00617\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_NONBASETHRDENA\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00618\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_NONBASETHRDENA\_Msk\ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CCR\_NONBASETHRDENA\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00619\ }
\DoxyCodeLine{00620\ \textcolor{comment}{/*\ SCB\ System\ Handler\ Control\ and\ State\ Register\ Definitions\ */}}
\DoxyCodeLine{00621\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00622\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00623\ }
\DoxyCodeLine{00624\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00625\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00626\ }
\DoxyCodeLine{00627\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00628\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MEMFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00629\ }
\DoxyCodeLine{00630\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLPENDED\_Pos\ \ \ \ \ \ \ \ \ 15U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00631\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLPENDED\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SVCALLPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00632\ }
\DoxyCodeLine{00633\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTPENDED\_Pos\ \ \ \ \ \ \ 14U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00634\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00635\ }
\DoxyCodeLine{00636\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTPENDED\_Pos\ \ \ \ \ \ \ 13U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00637\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MEMFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00638\ }
\DoxyCodeLine{00639\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTPENDED\_Pos\ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00640\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00641\ }
\DoxyCodeLine{00642\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SYSTICKACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00643\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SYSTICKACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SYSTICKACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00644\ }
\DoxyCodeLine{00645\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_PENDSVACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00646\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_PENDSVACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_PENDSVACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00647\ }
\DoxyCodeLine{00648\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00649\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MONITORACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00650\ }
\DoxyCodeLine{00651\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00652\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SVCALLACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00653\ }
\DoxyCodeLine{00654\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00655\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00656\ }
\DoxyCodeLine{00657\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00658\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00659\ }
\DoxyCodeLine{00660\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00661\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_SHCSR\_MEMFAULTACT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00662\ }
\DoxyCodeLine{00663\ \textcolor{comment}{/*\ SCB\ Configurable\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00664\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_USGFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00665\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_USGFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_CFSR\_USGFAULTSR\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00666\ }
\DoxyCodeLine{00667\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BUSFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00668\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BUSFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ SCB\_CFSR\_BUSFAULTSR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00669\ }
\DoxyCodeLine{00670\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MEMFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00671\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MEMFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ SCB\_CFSR\_MEMFAULTSR\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00672\ }
\DoxyCodeLine{00673\ \textcolor{comment}{/*\ MemManage\ Fault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00674\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MMARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 7U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00675\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MMARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MMARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00676\ }
\DoxyCodeLine{00677\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MLSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 5U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00678\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MLSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MLSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00679\ }
\DoxyCodeLine{00680\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00681\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00682\ }
\DoxyCodeLine{00683\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MUNSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00684\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MUNSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MUNSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00685\ }
\DoxyCodeLine{00686\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DACCVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00687\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DACCVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_DACCVIOL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00688\ }
\DoxyCodeLine{00689\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IACCVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00690\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IACCVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CFSR\_IACCVIOL\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00691\ }
\DoxyCodeLine{00692\ \textcolor{comment}{/*\ BusFault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00693\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BFARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 7U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00694\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BFARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_BFARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00695\ }
\DoxyCodeLine{00696\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_LSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 5U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00697\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_LSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_LSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00698\ }
\DoxyCodeLine{00699\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00700\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_STKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00701\ }
\DoxyCodeLine{00702\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00703\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00704\ }
\DoxyCodeLine{00705\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IMPRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 2U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00706\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IMPRECISERR\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_IMPRECISERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00707\ }
\DoxyCodeLine{00708\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_PRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00709\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_PRECISERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_PRECISERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00710\ }
\DoxyCodeLine{00711\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IBUSERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00712\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IBUSERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_IBUSERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00713\ }
\DoxyCodeLine{00714\ \textcolor{comment}{/*\ UsageFault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00715\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DIVBYZERO\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 9U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00716\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DIVBYZERO\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_DIVBYZERO\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00717\ }
\DoxyCodeLine{00718\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNALIGNED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 8U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00719\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNALIGNED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNALIGNED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00720\ }
\DoxyCodeLine{00721\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_NOCP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00722\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_NOCP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_NOCP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00723\ }
\DoxyCodeLine{00724\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVPC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 2U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00725\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVPC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_INVPC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00726\ }
\DoxyCodeLine{00727\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVSTATE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00728\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVSTATE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_INVSTATE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00729\ }
\DoxyCodeLine{00730\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNDEFINSTR\_Pos\ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00731\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNDEFINSTR\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNDEFINSTR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00732\ }
\DoxyCodeLine{00733\ \textcolor{comment}{/*\ SCB\ Hard\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00734\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_DEBUGEVT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00735\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_DEBUGEVT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_DEBUGEVT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00736\ }
\DoxyCodeLine{00737\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_FORCED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00738\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_FORCED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_FORCED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00739\ }
\DoxyCodeLine{00740\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_VECTTBL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00741\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_VECTTBL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_VECTTBL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00742\ }
\DoxyCodeLine{00743\ \textcolor{comment}{/*\ SCB\ Debug\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00744\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_EXTERNAL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00745\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_EXTERNAL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_EXTERNAL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00746\ }
\DoxyCodeLine{00747\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_VCATCH\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00748\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_VCATCH\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_VCATCH\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00749\ }
\DoxyCodeLine{00750\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_DWTTRAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00751\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_DWTTRAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_DWTTRAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00752\ }
\DoxyCodeLine{00753\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_BKPT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00754\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_BKPT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_BKPT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00755\ }
\DoxyCodeLine{00756\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_HALTED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00757\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_HALTED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_DFSR\_HALTED\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00758\ }
\DoxyCodeLine{00759\ \textcolor{comment}{/*\ SCB\ Cache\ Level\ ID\ Register\ Definitions\ */}}
\DoxyCodeLine{00760\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOUU\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00761\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOUU\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CLIDR\_LOUU\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00762\ }
\DoxyCodeLine{00763\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00764\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CLIDR\_LOC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00765\ }
\DoxyCodeLine{00766\ \textcolor{comment}{/*\ SCB\ Cache\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{00767\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_FORMAT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00768\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_FORMAT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CTR\_FORMAT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00769\ }
\DoxyCodeLine{00770\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_CWG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00771\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_CWG\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CTR\_CWG\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00772\ }
\DoxyCodeLine{00773\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_ERG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00774\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_ERG\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CTR\_ERG\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00775\ }
\DoxyCodeLine{00776\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_DMINLINE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00777\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_DMINLINE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CTR\_DMINLINE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00778\ }
\DoxyCodeLine{00779\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_IMINLINE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00780\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_IMINLINE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ SCB\_CTR\_IMINLINE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00781\ }
\DoxyCodeLine{00782\ \textcolor{comment}{/*\ SCB\ Cache\ Size\ ID\ Register\ Definitions\ */}}
\DoxyCodeLine{00783\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00784\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCSIDR\_WT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00785\ }
\DoxyCodeLine{00786\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WB\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00787\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WB\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCSIDR\_WB\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00788\ }
\DoxyCodeLine{00789\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_RA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00790\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_RA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCSIDR\_RA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00791\ }
\DoxyCodeLine{00792\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00793\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_WA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCSIDR\_WA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00794\ }
\DoxyCodeLine{00795\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_NUMSETS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 13U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00796\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_NUMSETS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFUL\ <<\ SCB\_CCSIDR\_NUMSETS\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00797\ }
\DoxyCodeLine{00798\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_ASSOCIATIVITY\_Pos\ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00799\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_ASSOCIATIVITY\_Msk\ \ \ \ \ \ \ (0x3FFUL\ <<\ SCB\_CCSIDR\_ASSOCIATIVITY\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00800\ }
\DoxyCodeLine{00801\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_LINESIZE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00802\ \textcolor{preprocessor}{\#define\ SCB\_CCSIDR\_LINESIZE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (7UL\ }\textcolor{comment}{/*<<\ SCB\_CCSIDR\_LINESIZE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00803\ }
\DoxyCodeLine{00804\ \textcolor{comment}{/*\ SCB\ Cache\ Size\ Selection\ Register\ Definitions\ */}}
\DoxyCodeLine{00805\ \textcolor{preprocessor}{\#define\ SCB\_CSSELR\_LEVEL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00806\ \textcolor{preprocessor}{\#define\ SCB\_CSSELR\_LEVEL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CSSELR\_LEVEL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00807\ }
\DoxyCodeLine{00808\ \textcolor{preprocessor}{\#define\ SCB\_CSSELR\_IND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00809\ \textcolor{preprocessor}{\#define\ SCB\_CSSELR\_IND\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CSSELR\_IND\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00810\ }
\DoxyCodeLine{00811\ \textcolor{comment}{/*\ SCB\ Software\ Triggered\ Interrupt\ Register\ Definitions\ */}}
\DoxyCodeLine{00812\ \textcolor{preprocessor}{\#define\ SCB\_STIR\_INTID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00813\ \textcolor{preprocessor}{\#define\ SCB\_STIR\_INTID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ }\textcolor{comment}{/*<<\ SCB\_STIR\_INTID\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00814\ }
\DoxyCodeLine{00815\ \textcolor{comment}{/*\ SCB\ D-\/Cache\ Invalidate\ by\ Set-\/way\ Register\ Definitions\ */}}
\DoxyCodeLine{00816\ \textcolor{preprocessor}{\#define\ SCB\_DCISW\_WAY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00817\ \textcolor{preprocessor}{\#define\ SCB\_DCISW\_WAY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ SCB\_DCISW\_WAY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00818\ }
\DoxyCodeLine{00819\ \textcolor{preprocessor}{\#define\ SCB\_DCISW\_SET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00820\ \textcolor{preprocessor}{\#define\ SCB\_DCISW\_SET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_DCISW\_SET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00821\ }
\DoxyCodeLine{00822\ \textcolor{comment}{/*\ SCB\ D-\/Cache\ Clean\ by\ Set-\/way\ Register\ Definitions\ */}}
\DoxyCodeLine{00823\ \textcolor{preprocessor}{\#define\ SCB\_DCCSW\_WAY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00824\ \textcolor{preprocessor}{\#define\ SCB\_DCCSW\_WAY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ SCB\_DCCSW\_WAY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00825\ }
\DoxyCodeLine{00826\ \textcolor{preprocessor}{\#define\ SCB\_DCCSW\_SET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00827\ \textcolor{preprocessor}{\#define\ SCB\_DCCSW\_SET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_DCCSW\_SET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00828\ }
\DoxyCodeLine{00829\ \textcolor{comment}{/*\ SCB\ D-\/Cache\ Clean\ and\ Invalidate\ by\ Set-\/way\ Register\ Definitions\ */}}
\DoxyCodeLine{00830\ \textcolor{preprocessor}{\#define\ SCB\_DCCISW\_WAY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00831\ \textcolor{preprocessor}{\#define\ SCB\_DCCISW\_WAY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ SCB\_DCCISW\_WAY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00832\ }
\DoxyCodeLine{00833\ \textcolor{preprocessor}{\#define\ SCB\_DCCISW\_SET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00834\ \textcolor{preprocessor}{\#define\ SCB\_DCCISW\_SET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_DCCISW\_SET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00835\ }
\DoxyCodeLine{00836\ \textcolor{comment}{/*\ Instruction\ Tightly-\/Coupled\ Memory\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00837\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_SZ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00838\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_SZ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_ITCMCR\_SZ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00839\ }
\DoxyCodeLine{00840\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_RETEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00841\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_RETEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ITCMCR\_RETEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00842\ }
\DoxyCodeLine{00843\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_RMW\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00844\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_RMW\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ITCMCR\_RMW\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00845\ }
\DoxyCodeLine{00846\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_EN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00847\ \textcolor{preprocessor}{\#define\ SCB\_ITCMCR\_EN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_ITCMCR\_EN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00848\ }
\DoxyCodeLine{00849\ \textcolor{comment}{/*\ Data\ Tightly-\/Coupled\ Memory\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00850\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_SZ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00851\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_SZ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_DTCMCR\_SZ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00852\ }
\DoxyCodeLine{00853\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_RETEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00854\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_RETEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DTCMCR\_RETEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00855\ }
\DoxyCodeLine{00856\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_RMW\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00857\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_RMW\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DTCMCR\_RMW\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00858\ }
\DoxyCodeLine{00859\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_EN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00860\ \textcolor{preprocessor}{\#define\ SCB\_DTCMCR\_EN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_DTCMCR\_EN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00861\ }
\DoxyCodeLine{00862\ \textcolor{comment}{/*\ AHBP\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00863\ \textcolor{preprocessor}{\#define\ SCB\_AHBPCR\_SZ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00864\ \textcolor{preprocessor}{\#define\ SCB\_AHBPCR\_SZ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_AHBPCR\_SZ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00865\ }
\DoxyCodeLine{00866\ \textcolor{preprocessor}{\#define\ SCB\_AHBPCR\_EN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00867\ \textcolor{preprocessor}{\#define\ SCB\_AHBPCR\_EN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_AHBPCR\_EN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00868\ }
\DoxyCodeLine{00869\ \textcolor{comment}{/*\ L1\ Cache\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00870\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_FORCEWT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00871\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_FORCEWT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CACR\_FORCEWT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00872\ }
\DoxyCodeLine{00873\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_ECCEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00874\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_ECCEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CACR\_ECCEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00875\ }
\DoxyCodeLine{00876\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_SIWT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00877\ \textcolor{preprocessor}{\#define\ SCB\_CACR\_SIWT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CACR\_SIWT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00878\ }
\DoxyCodeLine{00879\ \textcolor{comment}{/*\ AHBS\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00880\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_INITCOUNT\_Pos\ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00881\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_INITCOUNT\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ <<\ SCB\_AHBPCR\_INITCOUNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00882\ }
\DoxyCodeLine{00883\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_TPRI\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00884\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_TPRI\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFUL\ <<\ SCB\_AHBPCR\_TPRI\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00885\ }
\DoxyCodeLine{00886\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_CTL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00887\ \textcolor{preprocessor}{\#define\ SCB\_AHBSCR\_CTL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ }\textcolor{comment}{/*<<\ SCB\_AHBPCR\_CTL\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00888\ }
\DoxyCodeLine{00889\ \textcolor{comment}{/*\ Auxiliary\ Bus\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00890\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AXIMTYPE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00891\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AXIMTYPE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ SCB\_ABFSR\_AXIMTYPE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00892\ }
\DoxyCodeLine{00893\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_EPPB\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00894\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_EPPB\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ABFSR\_EPPB\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00895\ }
\DoxyCodeLine{00896\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AXIM\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00897\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AXIM\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ABFSR\_AXIM\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00898\ }
\DoxyCodeLine{00899\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AHBP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00900\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_AHBP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ABFSR\_AHBP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00901\ }
\DoxyCodeLine{00902\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_DTCM\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00903\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_DTCM\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ABFSR\_DTCM\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00904\ }
\DoxyCodeLine{00905\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_ITCM\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00906\ \textcolor{preprocessor}{\#define\ SCB\_ABFSR\_ITCM\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_ABFSR\_ITCM\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00907\ }
\DoxyCodeLine{00909\ }
\DoxyCodeLine{00910\ }
\DoxyCodeLine{00917\ }
\DoxyCodeLine{00921\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{00922\ \{}
\DoxyCodeLine{00923\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1U];}
\DoxyCodeLine{00924\ \ \ \_\_IM\ \ uint32\_t\ ICTR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00925\ \ \ \_\_IOM\ uint32\_t\ ACTLR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00926\ \}\ \mbox{\hyperlink{struct_s_cn_s_c_b___type}{SCnSCB\_Type}};}
\DoxyCodeLine{00927\ }
\DoxyCodeLine{00928\ \textcolor{comment}{/*\ Interrupt\ Controller\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{00929\ \textcolor{preprocessor}{\#define\ SCnSCB\_ICTR\_INTLINESNUM\_Pos\ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00930\ \textcolor{preprocessor}{\#define\ SCnSCB\_ICTR\_INTLINESNUM\_Msk\ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ SCnSCB\_ICTR\_INTLINESNUM\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00931\ }
\DoxyCodeLine{00932\ \textcolor{comment}{/*\ Auxiliary\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00933\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISDYNADD\_Pos\ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00934\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISDYNADD\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCnSCB\_ACTLR\_DISDYNADD\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00935\ }
\DoxyCodeLine{00936\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISISSCH1\_Pos\ \ \ \ \ \ \ \ \ 21U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00937\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISISSCH1\_Msk\ \ \ \ \ \ \ \ \ (0x1FUL\ <<\ SCnSCB\_ACTLR\_DISISSCH1\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00938\ }
\DoxyCodeLine{00939\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISDI\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00940\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISDI\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ <<\ SCnSCB\_ACTLR\_DISDI\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00941\ }
\DoxyCodeLine{00942\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISCRITAXIRUR\_Pos\ \ \ \ \ 15U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00943\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISCRITAXIRUR\_Msk\ \ \ \ \ (1UL\ <<\ SCnSCB\_ACTLR\_DISCRITAXIRUR\_Pos)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00944\ }
\DoxyCodeLine{00945\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISBTACALLOC\_Pos\ \ \ \ \ \ 14U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00946\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISBTACALLOC\_Msk\ \ \ \ \ \ (1UL\ <<\ SCnSCB\_ACTLR\_DISBTACALLOC\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00947\ }
\DoxyCodeLine{00948\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISBTACREAD\_Pos\ \ \ \ \ \ \ 13U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00949\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISBTACREAD\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCnSCB\_ACTLR\_DISBTACREAD\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00950\ }
\DoxyCodeLine{00951\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISITMATBFLUSH\_Pos\ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00952\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISITMATBFLUSH\_Msk\ \ \ \ (1UL\ <<\ SCnSCB\_ACTLR\_DISITMATBFLUSH\_Pos)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00953\ }
\DoxyCodeLine{00954\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISRAMODE\_Pos\ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00955\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISRAMODE\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCnSCB\_ACTLR\_DISRAMODE\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00956\ }
\DoxyCodeLine{00957\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_FPEXCODIS\_Pos\ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00958\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_FPEXCODIS\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCnSCB\_ACTLR\_FPEXCODIS\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00959\ }
\DoxyCodeLine{00960\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISFOLD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00961\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISFOLD\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCnSCB\_ACTLR\_DISFOLD\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00962\ }
\DoxyCodeLine{00963\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISMCYCINT\_Pos\ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00964\ \textcolor{preprocessor}{\#define\ SCnSCB\_ACTLR\_DISMCYCINT\_Msk\ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCnSCB\_ACTLR\_DISMCYCINT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00965\ }
\DoxyCodeLine{00967\ }
\DoxyCodeLine{00968\ }
\DoxyCodeLine{00975\ }
\DoxyCodeLine{00979\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{00980\ \{}
\DoxyCodeLine{00981\ \ \ \_\_IOM\ uint32\_t\ CTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00982\ \ \ \_\_IOM\ uint32\_t\ LOAD;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00983\ \ \ \_\_IOM\ uint32\_t\ VAL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00984\ \ \ \_\_IM\ \ uint32\_t\ CALIB;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00985\ \}\ \mbox{\hyperlink{struct_sys_tick___type}{SysTick\_Type}};}
\DoxyCodeLine{00986\ }
\DoxyCodeLine{00987\ \textcolor{comment}{/*\ SysTick\ Control\ /\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00988\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_COUNTFLAG\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00989\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_COUNTFLAG\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CTRL\_COUNTFLAG\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00990\ }
\DoxyCodeLine{00991\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_CLKSOURCE\_Pos\ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00992\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_CLKSOURCE\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CTRL\_CLKSOURCE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00993\ }
\DoxyCodeLine{00994\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_TICKINT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00995\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_TICKINT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CTRL\_TICKINT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00996\ }
\DoxyCodeLine{00997\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00998\ \textcolor{preprocessor}{\#define\ SysTick\_CTRL\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SysTick\_CTRL\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00999\ }
\DoxyCodeLine{01000\ \textcolor{comment}{/*\ SysTick\ Reload\ Register\ Definitions\ */}}
\DoxyCodeLine{01001\ \textcolor{preprocessor}{\#define\ SysTick\_LOAD\_RELOAD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01002\ \textcolor{preprocessor}{\#define\ SysTick\_LOAD\_RELOAD\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFFFUL\ }\textcolor{comment}{/*<<\ SysTick\_LOAD\_RELOAD\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01003\ }
\DoxyCodeLine{01004\ \textcolor{comment}{/*\ SysTick\ Current\ Register\ Definitions\ */}}
\DoxyCodeLine{01005\ \textcolor{preprocessor}{\#define\ SysTick\_VAL\_CURRENT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01006\ \textcolor{preprocessor}{\#define\ SysTick\_VAL\_CURRENT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFFFUL\ }\textcolor{comment}{/*<<\ SysTick\_VAL\_CURRENT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01007\ }
\DoxyCodeLine{01008\ \textcolor{comment}{/*\ SysTick\ Calibration\ Register\ Definitions\ */}}
\DoxyCodeLine{01009\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_NOREF\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01010\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_NOREF\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CALIB\_NOREF\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01011\ }
\DoxyCodeLine{01012\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_SKEW\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01013\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_SKEW\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SysTick\_CALIB\_SKEW\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01014\ }
\DoxyCodeLine{01015\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_TENMS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01016\ \textcolor{preprocessor}{\#define\ SysTick\_CALIB\_TENMS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFFFUL\ }\textcolor{comment}{/*<<\ SysTick\_CALIB\_TENMS\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01017\ }
\DoxyCodeLine{01019\ }
\DoxyCodeLine{01020\ }
\DoxyCodeLine{01027\ }
\DoxyCodeLine{01031\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01032\ \{}
\DoxyCodeLine{01033\ \ \ \_\_OM\ \ \textcolor{keyword}{union}}
\DoxyCodeLine{01034\ \ \ \{}
\DoxyCodeLine{01035\ \ \ \ \ \_\_OM\ \ uint8\_t\ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaf8ddc7a4238e8caa4dc16917b2e546ae}{u8}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01036\ \ \ \ \ \_\_OM\ \ uint16\_t\ \ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gafd6ee894932ae2539053f9064b8d4f9b}{u16}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01037\ \ \ \ \ \_\_OM\ \ uint32\_t\ \ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gacdf6f478ea57a840a8adbd1c05dcfdcf}{u32}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01038\ \ \ \}\ \ PORT\ [32U];\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01039\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[864U];}
\DoxyCodeLine{01040\ \ \ \_\_IOM\ uint32\_t\ TER;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01041\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[15U];}
\DoxyCodeLine{01042\ \ \ \_\_IOM\ uint32\_t\ TPR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01043\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[15U];}
\DoxyCodeLine{01044\ \ \ \_\_IOM\ uint32\_t\ TCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01045\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[32U];}
\DoxyCodeLine{01046\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[43U];}
\DoxyCodeLine{01047\ \ \ \_\_OM\ \ uint32\_t\ LAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01048\ \ \ \_\_IM\ \ uint32\_t\ LSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01049\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[6U];}
\DoxyCodeLine{01050\ \ \ \_\_IM\ \ uint32\_t\ PID4;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01051\ \ \ \_\_IM\ \ uint32\_t\ PID5;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01052\ \ \ \_\_IM\ \ uint32\_t\ PID6;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01053\ \ \ \_\_IM\ \ uint32\_t\ PID7;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01054\ \ \ \_\_IM\ \ uint32\_t\ PID0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01055\ \ \ \_\_IM\ \ uint32\_t\ PID1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01056\ \ \ \_\_IM\ \ uint32\_t\ PID2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01057\ \ \ \_\_IM\ \ uint32\_t\ PID3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01058\ \ \ \_\_IM\ \ uint32\_t\ CID0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01059\ \ \ \_\_IM\ \ uint32\_t\ CID1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01060\ \ \ \_\_IM\ \ uint32\_t\ CID2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01061\ \ \ \_\_IM\ \ uint32\_t\ CID3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01062\ \}\ \mbox{\hyperlink{struct_i_t_m___type}{ITM\_Type}};}
\DoxyCodeLine{01063\ }
\DoxyCodeLine{01064\ \textcolor{comment}{/*\ ITM\ Trace\ Privilege\ Register\ Definitions\ */}}
\DoxyCodeLine{01065\ \textcolor{preprocessor}{\#define\ ITM\_TPR\_PRIVMASK\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01066\ \textcolor{preprocessor}{\#define\ ITM\_TPR\_PRIVMASK\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFFFFFUL\ }\textcolor{comment}{/*<<\ ITM\_TPR\_PRIVMASK\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01067\ }
\DoxyCodeLine{01068\ \textcolor{comment}{/*\ ITM\ Trace\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01069\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_BUSY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 23U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01070\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_BUSY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_BUSY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01071\ }
\DoxyCodeLine{01072\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TraceBusID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01073\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TraceBusID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FUL\ <<\ ITM\_TCR\_TraceBusID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01074\ }
\DoxyCodeLine{01075\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_GTSFREQ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01076\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_GTSFREQ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ ITM\_TCR\_GTSFREQ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01077\ }
\DoxyCodeLine{01078\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TSPrescale\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01079\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TSPrescale\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ ITM\_TCR\_TSPrescale\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01080\ }
\DoxyCodeLine{01081\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_SWOENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01082\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_SWOENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_SWOENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01083\ }
\DoxyCodeLine{01084\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_DWTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01085\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_DWTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_DWTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01086\ }
\DoxyCodeLine{01087\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_SYNCENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01088\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_SYNCENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_SYNCENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01089\ }
\DoxyCodeLine{01090\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TSENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01091\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_TSENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_TCR\_TSENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01092\ }
\DoxyCodeLine{01093\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_ITMENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01094\ \textcolor{preprocessor}{\#define\ ITM\_TCR\_ITMENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ ITM\_TCR\_ITMENA\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01095\ }
\DoxyCodeLine{01096\ \textcolor{comment}{/*\ ITM\ Lock\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01097\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_ByteAcc\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01098\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_ByteAcc\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_LSR\_ByteAcc\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01099\ }
\DoxyCodeLine{01100\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_Access\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01101\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_Access\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ ITM\_LSR\_Access\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01102\ }
\DoxyCodeLine{01103\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_Present\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01104\ \textcolor{preprocessor}{\#define\ ITM\_LSR\_Present\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ ITM\_LSR\_Present\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01105\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_ITM\ */}}
\DoxyCodeLine{01107\ }
\DoxyCodeLine{01108\ }
\DoxyCodeLine{01115\ }
\DoxyCodeLine{01119\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01120\ \{}
\DoxyCodeLine{01121\ \ \ \_\_IOM\ uint32\_t\ CTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01122\ \ \ \_\_IOM\ uint32\_t\ CYCCNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01123\ \ \ \_\_IOM\ uint32\_t\ CPICNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01124\ \ \ \_\_IOM\ uint32\_t\ EXCCNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01125\ \ \ \_\_IOM\ uint32\_t\ SLEEPCNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01126\ \ \ \_\_IOM\ uint32\_t\ LSUCNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01127\ \ \ \_\_IOM\ uint32\_t\ FOLDCNT;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01128\ \ \ \_\_IM\ \ uint32\_t\ PCSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01129\ \ \ \_\_IOM\ uint32\_t\ COMP0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01130\ \ \ \_\_IOM\ uint32\_t\ MASK0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01131\ \ \ \_\_IOM\ uint32\_t\ FUNCTION0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01132\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1U];}
\DoxyCodeLine{01133\ \ \ \_\_IOM\ uint32\_t\ COMP1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01134\ \ \ \_\_IOM\ uint32\_t\ MASK1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01135\ \ \ \_\_IOM\ uint32\_t\ FUNCTION1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01136\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[1U];}
\DoxyCodeLine{01137\ \ \ \_\_IOM\ uint32\_t\ COMP2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01138\ \ \ \_\_IOM\ uint32\_t\ MASK2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01139\ \ \ \_\_IOM\ uint32\_t\ FUNCTION2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01140\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[1U];}
\DoxyCodeLine{01141\ \ \ \_\_IOM\ uint32\_t\ COMP3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01142\ \ \ \_\_IOM\ uint32\_t\ MASK3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01143\ \ \ \_\_IOM\ uint32\_t\ FUNCTION3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01144\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[981U];}
\DoxyCodeLine{01145\ \ \ \_\_OM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4b8037802a3b25e367f0977d86f754ad}{LAR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01146\ \ \ \_\_IM\ \ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga4281befcc19ee69afdd50801cb1c9bcf}{LSR}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01147\ \}\ \mbox{\hyperlink{struct_d_w_t___type}{DWT\_Type}};}
\DoxyCodeLine{01148\ }
\DoxyCodeLine{01149\ \textcolor{comment}{/*\ DWT\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01150\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NUMCOMP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01151\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NUMCOMP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_NUMCOMP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01152\ }
\DoxyCodeLine{01153\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOTRCPKT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01154\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOTRCPKT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOTRCPKT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01155\ }
\DoxyCodeLine{01156\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOEXTTRIG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01157\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOEXTTRIG\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOEXTTRIG\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01158\ }
\DoxyCodeLine{01159\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOCYCCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01160\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOCYCCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOCYCCNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01161\ }
\DoxyCodeLine{01162\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOPRFCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01163\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_NOPRFCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_NOPRFCNT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01164\ }
\DoxyCodeLine{01165\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01166\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01167\ }
\DoxyCodeLine{01168\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 21U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01169\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_FOLDEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01170\ }
\DoxyCodeLine{01171\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01172\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_LSUEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01173\ }
\DoxyCodeLine{01174\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01175\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_SLEEPEVTENA\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01176\ }
\DoxyCodeLine{01177\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01178\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01179\ }
\DoxyCodeLine{01180\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01181\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CPIEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01182\ }
\DoxyCodeLine{01183\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01184\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCTRCENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01185\ }
\DoxyCodeLine{01186\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01187\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_PCSAMPLENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01188\ }
\DoxyCodeLine{01189\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01190\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_CTRL\_SYNCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01191\ }
\DoxyCodeLine{01192\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01193\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01194\ }
\DoxyCodeLine{01195\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01196\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTINIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01197\ }
\DoxyCodeLine{01198\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01199\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTPRESET\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01200\ }
\DoxyCodeLine{01201\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01202\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ DWT\_CTRL\_CYCCNTENA\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01203\ }
\DoxyCodeLine{01204\ \textcolor{comment}{/*\ DWT\ CPI\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01205\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01206\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_CPICNT\_CPICNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01207\ }
\DoxyCodeLine{01208\ \textcolor{comment}{/*\ DWT\ Exception\ Overhead\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01209\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01210\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_EXCCNT\_EXCCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01211\ }
\DoxyCodeLine{01212\ \textcolor{comment}{/*\ DWT\ Sleep\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01213\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01214\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01215\ }
\DoxyCodeLine{01216\ \textcolor{comment}{/*\ DWT\ LSU\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01217\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01218\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_LSUCNT\_LSUCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01219\ }
\DoxyCodeLine{01220\ \textcolor{comment}{/*\ DWT\ Folded-\/instruction\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01221\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01222\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_FOLDCNT\_FOLDCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01223\ }
\DoxyCodeLine{01224\ \textcolor{comment}{/*\ DWT\ Comparator\ Mask\ Register\ Definitions\ */}}
\DoxyCodeLine{01225\ \textcolor{preprocessor}{\#define\ DWT\_MASK\_MASK\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01226\ \textcolor{preprocessor}{\#define\ DWT\_MASK\_MASK\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ }\textcolor{comment}{/*<<\ DWT\_MASK\_MASK\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01227\ }
\DoxyCodeLine{01228\ \textcolor{comment}{/*\ DWT\ Comparator\ Function\ Register\ Definitions\ */}}
\DoxyCodeLine{01229\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCHED\_Pos\ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01230\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCHED\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_MATCHED\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01231\ }
\DoxyCodeLine{01232\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR1\_Pos\ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01233\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR1\_Msk\ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_FUNCTION\_DATAVADDR1\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01234\ }
\DoxyCodeLine{01235\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR0\_Pos\ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01236\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVADDR0\_Msk\ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_FUNCTION\_DATAVADDR0\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01237\ }
\DoxyCodeLine{01238\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Pos\ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01239\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Msk\ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_FUNCTION\_DATAVSIZE\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01240\ }
\DoxyCodeLine{01241\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_LNK1ENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01242\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_LNK1ENA\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_LNK1ENA\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01243\ }
\DoxyCodeLine{01244\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVMATCH\_Pos\ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01245\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVMATCH\_Msk\ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_DATAVMATCH\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01246\ }
\DoxyCodeLine{01247\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_CYCMATCH\_Pos\ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01248\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_CYCMATCH\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_CYCMATCH\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01249\ }
\DoxyCodeLine{01250\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_EMITRANGE\_Pos\ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01251\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_EMITRANGE\_Msk\ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_EMITRANGE\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01252\ }
\DoxyCodeLine{01253\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_FUNCTION\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01254\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_FUNCTION\_Msk\ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ DWT\_FUNCTION\_FUNCTION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01255\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_DWT\ */}}
\DoxyCodeLine{01257\ }
\DoxyCodeLine{01258\ }
\DoxyCodeLine{01265\ }
\DoxyCodeLine{01269\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01270\ \{}
\DoxyCodeLine{01271\ \ \ \_\_IM\ \ uint32\_t\ SSPSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01272\ \ \ \_\_IOM\ uint32\_t\ CSPSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01273\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[2U];}
\DoxyCodeLine{01274\ \ \ \_\_IOM\ uint32\_t\ ACPR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01275\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[55U];}
\DoxyCodeLine{01276\ \ \ \_\_IOM\ uint32\_t\ SPPR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01277\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[131U];}
\DoxyCodeLine{01278\ \ \ \_\_IM\ \ uint32\_t\ FFSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01279\ \ \ \_\_IOM\ uint32\_t\ FFCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01280\ \ \ \_\_IM\ \ uint32\_t\ FSCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01281\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[759U];}
\DoxyCodeLine{01282\ \ \ \_\_IM\ \ uint32\_t\ TRIGGER;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01283\ \ \ \_\_IM\ \ uint32\_t\ FIFO0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01284\ \ \ \_\_IM\ \ uint32\_t\ ITATBCTR2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01285\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[1U];}
\DoxyCodeLine{01286\ \ \ \_\_IM\ \ uint32\_t\ ITATBCTR0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01287\ \ \ \_\_IM\ \ uint32\_t\ FIFO1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01288\ \ \ \_\_IOM\ uint32\_t\ ITCTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01289\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[39U];}
\DoxyCodeLine{01290\ \ \ \_\_IOM\ uint32\_t\ CLAIMSET;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01291\ \ \ \_\_IOM\ uint32\_t\ CLAIMCLR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01292\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED7[8U];}
\DoxyCodeLine{01293\ \ \ \_\_IM\ \ uint32\_t\ DEVID;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01294\ \ \ \_\_IM\ \ uint32\_t\ DEVTYPE;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01295\ \}\ \mbox{\hyperlink{struct_t_p_i___type}{TPI\_Type}};}
\DoxyCodeLine{01296\ }
\DoxyCodeLine{01297\ \textcolor{comment}{/*\ TPI\ Asynchronous\ Clock\ Prescaler\ Register\ Definitions\ */}}
\DoxyCodeLine{01298\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01299\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFUL\ }\textcolor{comment}{/*<<\ TPI\_ACPR\_PRESCALER\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01300\ }
\DoxyCodeLine{01301\ \textcolor{comment}{/*\ TPI\ Selected\ Pin\ Protocol\ Register\ Definitions\ */}}
\DoxyCodeLine{01302\ \textcolor{preprocessor}{\#define\ TPI\_SPPR\_TXMODE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01303\ \textcolor{preprocessor}{\#define\ TPI\_SPPR\_TXMODE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ }\textcolor{comment}{/*<<\ TPI\_SPPR\_TXMODE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01304\ }
\DoxyCodeLine{01305\ \textcolor{comment}{/*\ TPI\ Formatter\ and\ Flush\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01306\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtNonStop\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01307\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtNonStop\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_FtNonStop\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01308\ }
\DoxyCodeLine{01309\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_TCPresent\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01310\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_TCPresent\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_TCPresent\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01311\ }
\DoxyCodeLine{01312\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtStopped\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01313\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtStopped\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_FtStopped\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01314\ }
\DoxyCodeLine{01315\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FlInProg\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01316\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FlInProg\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_FFSR\_FlInProg\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01317\ }
\DoxyCodeLine{01318\ \textcolor{comment}{/*\ TPI\ Formatter\ and\ Flush\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01319\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_TrigIn\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01320\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_TrigIn\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFCR\_TrigIn\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01321\ }
\DoxyCodeLine{01322\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_EnFCont\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01323\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_EnFCont\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFCR\_EnFCont\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01324\ }
\DoxyCodeLine{01325\ \textcolor{comment}{/*\ TPI\ TRIGGER\ Register\ Definitions\ */}}
\DoxyCodeLine{01326\ \textcolor{preprocessor}{\#define\ TPI\_TRIGGER\_TRIGGER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01327\ \textcolor{preprocessor}{\#define\ TPI\_TRIGGER\_TRIGGER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_TRIGGER\_TRIGGER\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01328\ }
\DoxyCodeLine{01329\ \textcolor{comment}{/*\ TPI\ Integration\ ETM\ Data\ Register\ Definitions\ (FIFO0)\ */}}
\DoxyCodeLine{01330\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01331\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FIFO0\_ITM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01332\ }
\DoxyCodeLine{01333\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_bytecount\_Pos\ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01334\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ITM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO0\_ITM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01335\ }
\DoxyCodeLine{01336\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01337\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FIFO0\_ETM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01338\ }
\DoxyCodeLine{01339\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_bytecount\_Pos\ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01340\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO0\_ETM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01341\ }
\DoxyCodeLine{01342\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM2\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01343\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM2\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO0\_ETM2\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01344\ }
\DoxyCodeLine{01345\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM1\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01346\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM1\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO0\_ETM1\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01347\ }
\DoxyCodeLine{01348\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM0\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01349\ \textcolor{preprocessor}{\#define\ TPI\_FIFO0\_ETM0\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ TPI\_FIFO0\_ETM0\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01350\ }
\DoxyCodeLine{01351\ \textcolor{comment}{/*\ TPI\ ITATBCTR2\ Register\ Definitions\ */}}
\DoxyCodeLine{01352\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY2\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01353\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY2\_Msk\ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_ITATBCTR2\_ATREADY2\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01354\ }
\DoxyCodeLine{01355\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY1\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01356\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR2\_ATREADY1\_Msk\ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_ITATBCTR2\_ATREADY1\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01357\ }
\DoxyCodeLine{01358\ \textcolor{comment}{/*\ TPI\ Integration\ ITM\ Data\ Register\ Definitions\ (FIFO1)\ */}}
\DoxyCodeLine{01359\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01360\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FIFO1\_ITM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01361\ }
\DoxyCodeLine{01362\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_bytecount\_Pos\ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01363\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO1\_ITM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01364\ }
\DoxyCodeLine{01365\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_ATVALID\_Pos\ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01366\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_ATVALID\_Msk\ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FIFO1\_ETM\_ATVALID\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01367\ }
\DoxyCodeLine{01368\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_bytecount\_Pos\ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01369\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ETM\_bytecount\_Msk\ \ \ \ \ \ \ \ (0x3UL\ <<\ TPI\_FIFO1\_ETM\_bytecount\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01370\ }
\DoxyCodeLine{01371\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM2\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01372\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM2\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO1\_ITM2\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01373\ }
\DoxyCodeLine{01374\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM1\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01375\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM1\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ TPI\_FIFO1\_ITM1\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01376\ }
\DoxyCodeLine{01377\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM0\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01378\ \textcolor{preprocessor}{\#define\ TPI\_FIFO1\_ITM0\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ TPI\_FIFO1\_ITM0\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01379\ }
\DoxyCodeLine{01380\ \textcolor{comment}{/*\ TPI\ ITATBCTR0\ Register\ Definitions\ */}}
\DoxyCodeLine{01381\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR0\_ATREADY2\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01382\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR0\_ATREADY2\_Msk\ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_ITATBCTR0\_ATREADY2\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01383\ }
\DoxyCodeLine{01384\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR0\_ATREADY1\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01385\ \textcolor{preprocessor}{\#define\ TPI\_ITATBCTR0\_ATREADY1\_Msk\ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_ITATBCTR0\_ATREADY1\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01386\ }
\DoxyCodeLine{01387\ \textcolor{comment}{/*\ TPI\ Integration\ Mode\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01388\ \textcolor{preprocessor}{\#define\ TPI\_ITCTRL\_Mode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01389\ \textcolor{preprocessor}{\#define\ TPI\_ITCTRL\_Mode\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ }\textcolor{comment}{/*<<\ TPI\_ITCTRL\_Mode\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01390\ }
\DoxyCodeLine{01391\ \textcolor{comment}{/*\ TPI\ DEVID\ Register\ Definitions\ */}}
\DoxyCodeLine{01392\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NRZVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01393\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NRZVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_DEVID\_NRZVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01394\ }
\DoxyCodeLine{01395\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MANCVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01396\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MANCVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_DEVID\_MANCVALID\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01397\ }
\DoxyCodeLine{01398\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_PTINVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01399\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_PTINVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_DEVID\_PTINVALID\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01400\ }
\DoxyCodeLine{01401\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MinBufSz\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01402\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_MinBufSz\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x7UL\ <<\ TPI\_DEVID\_MinBufSz\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01403\ }
\DoxyCodeLine{01404\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_AsynClkIn\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01405\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_AsynClkIn\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_DEVID\_AsynClkIn\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01406\ }
\DoxyCodeLine{01407\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NrTraceInput\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01408\ \textcolor{preprocessor}{\#define\ TPI\_DEVID\_NrTraceInput\_Msk\ \ \ \ \ \ \ \ \ (0x1FUL\ }\textcolor{comment}{/*<<\ TPI\_DEVID\_NrTraceInput\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01409\ }
\DoxyCodeLine{01410\ \textcolor{comment}{/*\ TPI\ DEVTYPE\ Register\ Definitions\ */}}
\DoxyCodeLine{01411\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_SubType\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01412\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_SubType\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ TPI\_DEVTYPE\_SubType\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01413\ }
\DoxyCodeLine{01414\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_MajorType\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01415\ \textcolor{preprocessor}{\#define\ TPI\_DEVTYPE\_MajorType\_Msk\ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ TPI\_DEVTYPE\_MajorType\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01416\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_TPI\ */}}
\DoxyCodeLine{01418\ }
\DoxyCodeLine{01419\ }
\DoxyCodeLine{01420\ \textcolor{preprocessor}{\#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01427\ }
\DoxyCodeLine{01431\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01432\ \{}
\DoxyCodeLine{01433\ \ \ \_\_IM\ \ uint32\_t\ TYPE;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01434\ \ \ \_\_IOM\ uint32\_t\ CTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01435\ \ \ \_\_IOM\ uint32\_t\ RNR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01436\ \ \ \_\_IOM\ uint32\_t\ RBAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01437\ \ \ \_\_IOM\ uint32\_t\ RASR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01438\ \ \ \_\_IOM\ uint32\_t\ RBAR\_A1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01439\ \ \ \_\_IOM\ uint32\_t\ RASR\_A1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01440\ \ \ \_\_IOM\ uint32\_t\ RBAR\_A2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01441\ \ \ \_\_IOM\ uint32\_t\ RASR\_A2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01442\ \ \ \_\_IOM\ uint32\_t\ RBAR\_A3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01443\ \ \ \_\_IOM\ uint32\_t\ RASR\_A3;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01444\ \}\ \mbox{\hyperlink{struct_m_p_u___type}{MPU\_Type}};}
\DoxyCodeLine{01445\ }
\DoxyCodeLine{01446\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_RALIASES\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U}}
\DoxyCodeLine{01447\ }
\DoxyCodeLine{01448\ \textcolor{comment}{/*\ MPU\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{01449\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_IREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01450\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_IREGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_TYPE\_IREGION\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01451\ }
\DoxyCodeLine{01452\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_DREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01453\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_DREGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_TYPE\_DREGION\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01454\ }
\DoxyCodeLine{01455\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_SEPARATE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01456\ \textcolor{preprocessor}{\#define\ MPU\_TYPE\_SEPARATE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_TYPE\_SEPARATE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01457\ }
\DoxyCodeLine{01458\ \textcolor{comment}{/*\ MPU\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01459\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_PRIVDEFENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01460\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_PRIVDEFENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_CTRL\_PRIVDEFENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01461\ }
\DoxyCodeLine{01462\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_HFNMIENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01463\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_HFNMIENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_CTRL\_HFNMIENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01464\ }
\DoxyCodeLine{01465\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01466\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_CTRL\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01467\ }
\DoxyCodeLine{01468\ \textcolor{comment}{/*\ MPU\ Region\ Number\ Register\ Definitions\ */}}
\DoxyCodeLine{01469\ \textcolor{preprocessor}{\#define\ MPU\_RNR\_REGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01470\ \textcolor{preprocessor}{\#define\ MPU\_RNR\_REGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ MPU\_RNR\_REGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01471\ }
\DoxyCodeLine{01472\ \textcolor{comment}{/*\ MPU\ Region\ Base\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01473\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_ADDR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01474\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_ADDR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ MPU\_RBAR\_ADDR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01475\ }
\DoxyCodeLine{01476\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_VALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01477\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_VALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RBAR\_VALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01478\ }
\DoxyCodeLine{01479\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_REGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01480\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_REGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ MPU\_RBAR\_REGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01481\ }
\DoxyCodeLine{01482\ \textcolor{comment}{/*\ MPU\ Region\ Attribute\ and\ Size\ Register\ Definitions\ */}}
\DoxyCodeLine{01483\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_ATTRS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01484\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_ATTRS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ MPU\_RASR\_ATTRS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01485\ }
\DoxyCodeLine{01486\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_XN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01487\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_XN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RASR\_XN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01488\ }
\DoxyCodeLine{01489\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_AP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01490\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_AP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7UL\ <<\ MPU\_RASR\_AP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01491\ }
\DoxyCodeLine{01492\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_TEX\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01493\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_TEX\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7UL\ <<\ MPU\_RASR\_TEX\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01494\ }
\DoxyCodeLine{01495\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_S\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01496\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_S\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RASR\_S\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01497\ }
\DoxyCodeLine{01498\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_C\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01499\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_C\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RASR\_C\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01500\ }
\DoxyCodeLine{01501\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_B\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01502\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_B\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_RASR\_B\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01503\ }
\DoxyCodeLine{01504\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_SRD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01505\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_SRD\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_RASR\_SRD\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01506\ }
\DoxyCodeLine{01507\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_SIZE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01508\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_SIZE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ <<\ MPU\_RASR\_SIZE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01509\ }
\DoxyCodeLine{01510\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01511\ \textcolor{preprocessor}{\#define\ MPU\_RASR\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_RASR\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01512\ }
\DoxyCodeLine{01514\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01515\ }
\DoxyCodeLine{01516\ }
\DoxyCodeLine{01523\ }
\DoxyCodeLine{01527\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01528\ \{}
\DoxyCodeLine{01529\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1U];}
\DoxyCodeLine{01530\ \ \ \_\_IOM\ uint32\_t\ FPCCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01531\ \ \ \_\_IOM\ uint32\_t\ FPCAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01532\ \ \ \_\_IOM\ uint32\_t\ FPDSCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01533\ \ \ \_\_IM\ \ uint32\_t\ MVFR0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01534\ \ \ \_\_IM\ \ uint32\_t\ MVFR1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01535\ \ \ \_\_IM\ \ uint32\_t\ MVFR2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01536\ \}\ \mbox{\hyperlink{struct_f_p_u___type}{FPU\_Type}};}
\DoxyCodeLine{01537\ }
\DoxyCodeLine{01538\ \textcolor{comment}{/*\ Floating-\/Point\ Context\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01539\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_ASPEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01540\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_ASPEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_ASPEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01541\ }
\DoxyCodeLine{01542\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01543\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_LSPEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01544\ }
\DoxyCodeLine{01545\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MONRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01546\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MONRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_MONRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01547\ }
\DoxyCodeLine{01548\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_BFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01549\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_BFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_BFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01550\ }
\DoxyCodeLine{01551\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MMRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01552\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MMRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_MMRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01553\ }
\DoxyCodeLine{01554\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_HFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01555\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_HFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_HFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01556\ }
\DoxyCodeLine{01557\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_THREAD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01558\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_THREAD\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_THREAD\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01559\ }
\DoxyCodeLine{01560\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_USER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01561\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_USER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_USER\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01562\ }
\DoxyCodeLine{01563\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01564\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ FPU\_FPCCR\_LSPACT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01565\ }
\DoxyCodeLine{01566\ \textcolor{comment}{/*\ Floating-\/Point\ Context\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01567\ \textcolor{preprocessor}{\#define\ FPU\_FPCAR\_ADDRESS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01568\ \textcolor{preprocessor}{\#define\ FPU\_FPCAR\_ADDRESS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFFFFFUL\ <<\ FPU\_FPCAR\_ADDRESS\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01569\ }
\DoxyCodeLine{01570\ \textcolor{comment}{/*\ Floating-\/Point\ Default\ Status\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01571\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_AHP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01572\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_AHP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPDSCR\_AHP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01573\ }
\DoxyCodeLine{01574\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_DN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01575\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_DN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPDSCR\_DN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01576\ }
\DoxyCodeLine{01577\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_FZ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01578\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_FZ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPDSCR\_FZ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01579\ }
\DoxyCodeLine{01580\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_RMode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01581\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_RMode\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ FPU\_FPDSCR\_RMode\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01582\ }
\DoxyCodeLine{01583\ \textcolor{comment}{/*\ Media\ and\ FP\ Feature\ Register\ 0\ Definitions\ */}}
\DoxyCodeLine{01584\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_rounding\_modes\_Pos\ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01585\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_rounding\_modes\_Msk\ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_FP\_rounding\_modes\_Pos)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01586\ }
\DoxyCodeLine{01587\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Short\_vectors\_Pos\ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01588\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Short\_vectors\_Msk\ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Short\_vectors\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01589\ }
\DoxyCodeLine{01590\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Square\_root\_Pos\ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01591\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Square\_root\_Msk\ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Square\_root\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01592\ }
\DoxyCodeLine{01593\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Divide\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01594\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Divide\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Divide\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01595\ }
\DoxyCodeLine{01596\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_excep\_trapping\_Pos\ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01597\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_excep\_trapping\_Msk\ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_FP\_excep\_trapping\_Pos)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01598\ }
\DoxyCodeLine{01599\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Double\_precision\_Pos\ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01600\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Double\_precision\_Msk\ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Double\_precision\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01601\ }
\DoxyCodeLine{01602\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Single\_precision\_Pos\ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01603\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Single\_precision\_Msk\ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Single\_precision\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01604\ }
\DoxyCodeLine{01605\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_A\_SIMD\_registers\_Pos\ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01606\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_A\_SIMD\_registers\_Msk\ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ FPU\_MVFR0\_A\_SIMD\_registers\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01607\ }
\DoxyCodeLine{01608\ \textcolor{comment}{/*\ Media\ and\ FP\ Feature\ Register\ 1\ Definitions\ */}}
\DoxyCodeLine{01609\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_fused\_MAC\_Pos\ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01610\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_fused\_MAC\_Msk\ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR1\_FP\_fused\_MAC\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01611\ }
\DoxyCodeLine{01612\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_HPFP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01613\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_HPFP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR1\_FP\_HPFP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01614\ }
\DoxyCodeLine{01615\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_D\_NaN\_mode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01616\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_D\_NaN\_mode\_Msk\ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR1\_D\_NaN\_mode\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01617\ }
\DoxyCodeLine{01618\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FtZ\_mode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01619\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FtZ\_mode\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ FPU\_MVFR1\_FtZ\_mode\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01620\ }
\DoxyCodeLine{01621\ \textcolor{comment}{/*\ Media\ and\ FP\ Feature\ Register\ 2\ Definitions\ */}}
\DoxyCodeLine{01622\ }
\DoxyCodeLine{01623\ \textcolor{preprocessor}{\#define\ FPU\_MVFR2\_VFP\_Misc\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01624\ \textcolor{preprocessor}{\#define\ FPU\_MVFR2\_VFP\_Misc\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR2\_VFP\_Misc\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01625\ }
\DoxyCodeLine{01627\ }
\DoxyCodeLine{01628\ }
\DoxyCodeLine{01635\ }
\DoxyCodeLine{01639\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01640\ \{}
\DoxyCodeLine{01641\ \ \ \_\_IOM\ uint32\_t\ DHCSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01642\ \ \ \_\_OM\ \ uint32\_t\ DCRSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01643\ \ \ \_\_IOM\ uint32\_t\ DCRDR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01644\ \ \ \_\_IOM\ uint32\_t\ DEMCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01645\ \}\ \mbox{\hyperlink{struct_core_debug___type}{CoreDebug\_Type}};}
\DoxyCodeLine{01646\ }
\DoxyCodeLine{01647\ \textcolor{comment}{/*\ Debug\ Halting\ Control\ and\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01648\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_DBGKEY\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01649\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_DBGKEY\_Msk\ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ CoreDebug\_DHCSR\_DBGKEY\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01650\ }
\DoxyCodeLine{01651\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RESET\_ST\_Pos\ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01652\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RESET\_ST\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_RESET\_ST\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01653\ }
\DoxyCodeLine{01654\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RETIRE\_ST\_Pos\ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01655\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_RETIRE\_ST\_Msk\ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_RETIRE\_ST\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01656\ }
\DoxyCodeLine{01657\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_LOCKUP\_Pos\ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01658\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_LOCKUP\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_LOCKUP\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01659\ }
\DoxyCodeLine{01660\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_SLEEP\_Pos\ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01661\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_SLEEP\_Msk\ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_SLEEP\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01662\ }
\DoxyCodeLine{01663\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_HALT\_Pos\ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01664\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_HALT\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_HALT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01665\ }
\DoxyCodeLine{01666\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_REGRDY\_Pos\ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01667\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_S\_REGRDY\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_S\_REGRDY\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01668\ }
\DoxyCodeLine{01669\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_SNAPSTALL\_Pos\ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01670\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_SNAPSTALL\_Msk\ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_C\_SNAPSTALL\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01671\ }
\DoxyCodeLine{01672\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_MASKINTS\_Pos\ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01673\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_MASKINTS\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_C\_MASKINTS\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01674\ }
\DoxyCodeLine{01675\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_STEP\_Pos\ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01676\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_STEP\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_C\_STEP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01677\ }
\DoxyCodeLine{01678\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_HALT\_Pos\ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01679\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_HALT\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DHCSR\_C\_HALT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01680\ }
\DoxyCodeLine{01681\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_DEBUGEN\_Pos\ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01682\ \textcolor{preprocessor}{\#define\ CoreDebug\_DHCSR\_C\_DEBUGEN\_Msk\ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ CoreDebug\_DHCSR\_C\_DEBUGEN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01683\ }
\DoxyCodeLine{01684\ \textcolor{comment}{/*\ Debug\ Core\ Register\ Selector\ Register\ Definitions\ */}}
\DoxyCodeLine{01685\ \textcolor{preprocessor}{\#define\ CoreDebug\_DCRSR\_REGWnR\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01686\ \textcolor{preprocessor}{\#define\ CoreDebug\_DCRSR\_REGWnR\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DCRSR\_REGWnR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01687\ }
\DoxyCodeLine{01688\ \textcolor{preprocessor}{\#define\ CoreDebug\_DCRSR\_REGSEL\_Pos\ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01689\ \textcolor{preprocessor}{\#define\ CoreDebug\_DCRSR\_REGSEL\_Msk\ \ \ \ \ \ \ \ \ (0x1FUL\ }\textcolor{comment}{/*<<\ CoreDebug\_DCRSR\_REGSEL\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01690\ }
\DoxyCodeLine{01691\ \textcolor{comment}{/*\ Debug\ Exception\ and\ Monitor\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01692\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_TRCENA\_Pos\ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01693\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_TRCENA\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_TRCENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01694\ }
\DoxyCodeLine{01695\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_REQ\_Pos\ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01696\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_REQ\_Msk\ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_MON\_REQ\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01697\ }
\DoxyCodeLine{01698\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_STEP\_Pos\ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01699\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_STEP\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_MON\_STEP\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01700\ }
\DoxyCodeLine{01701\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_PEND\_Pos\ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01702\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_PEND\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_MON\_PEND\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01703\ }
\DoxyCodeLine{01704\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_EN\_Pos\ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01705\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_MON\_EN\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_MON\_EN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01706\ }
\DoxyCodeLine{01707\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_HARDERR\_Pos\ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01708\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_HARDERR\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_HARDERR\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01709\ }
\DoxyCodeLine{01710\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_INTERR\_Pos\ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01711\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_INTERR\_Msk\ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_INTERR\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01712\ }
\DoxyCodeLine{01713\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_BUSERR\_Pos\ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01714\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_BUSERR\_Msk\ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_BUSERR\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01715\ }
\DoxyCodeLine{01716\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_STATERR\_Pos\ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01717\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_STATERR\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_STATERR\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01718\ }
\DoxyCodeLine{01719\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_CHKERR\_Pos\ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01720\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_CHKERR\_Msk\ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_CHKERR\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01721\ }
\DoxyCodeLine{01722\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_NOCPERR\_Pos\ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01723\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_NOCPERR\_Msk\ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_NOCPERR\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01724\ }
\DoxyCodeLine{01725\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_MMERR\_Pos\ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01726\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_MMERR\_Msk\ \ \ \ \ \ \ (1UL\ <<\ CoreDebug\_DEMCR\_VC\_MMERR\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01727\ }
\DoxyCodeLine{01728\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_CORERESET\_Pos\ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01729\ \textcolor{preprocessor}{\#define\ CoreDebug\_DEMCR\_VC\_CORERESET\_Msk\ \ \ (1UL\ }\textcolor{comment}{/*<<\ CoreDebug\_DEMCR\_VC\_CORERESET\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01730\ }
\DoxyCodeLine{01732\ }
\DoxyCodeLine{01733\ }
\DoxyCodeLine{01740\ }
\DoxyCodeLine{01747\ \textcolor{preprocessor}{\#define\ \_VAL2FLD(field,\ value)\ \ \ \ (((uint32\_t)(value)\ <<\ field\ \#\#\ \_Pos)\ \&\ field\ \#\#\ \_Msk)}}
\DoxyCodeLine{01748\ }
\DoxyCodeLine{01755\ \textcolor{preprocessor}{\#define\ \_FLD2VAL(field,\ value)\ \ \ \ (((uint32\_t)(value)\ \&\ field\ \#\#\ \_Msk)\ >>\ field\ \#\#\ \_Pos)}}
\DoxyCodeLine{01756\ }
\DoxyCodeLine{01758\ }
\DoxyCodeLine{01759\ }
\DoxyCodeLine{01766\ }
\DoxyCodeLine{01767\ \textcolor{comment}{/*\ Memory\ mapping\ of\ Core\ Hardware\ */}}
\DoxyCodeLine{01768\ \textcolor{preprocessor}{\#define\ SCS\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE000E000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01769\ \textcolor{preprocessor}{\#define\ ITM\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE0000000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01770\ \textcolor{preprocessor}{\#define\ DWT\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE0001000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01771\ \textcolor{preprocessor}{\#define\ TPI\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (0xE0040000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01772\ \textcolor{preprocessor}{\#define\ CoreDebug\_BASE\ \ \ \ \ \ (0xE000EDF0UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01773\ \textcolor{preprocessor}{\#define\ SysTick\_BASE\ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0010UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01774\ \textcolor{preprocessor}{\#define\ NVIC\_BASE\ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0100UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01775\ \textcolor{preprocessor}{\#define\ SCB\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0D00UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01776\ }
\DoxyCodeLine{01777\ \textcolor{preprocessor}{\#define\ SCnSCB\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SCnSCB\_Type\ \ \ \ *)\ \ \ \ \ SCS\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01778\ \textcolor{preprocessor}{\#define\ SCB\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SCB\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ SCB\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01779\ \textcolor{preprocessor}{\#define\ SysTick\ \ \ \ \ \ \ \ \ \ \ \ \ ((SysTick\_Type\ \ \ *)\ \ \ \ \ SysTick\_BASE\ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01780\ \textcolor{preprocessor}{\#define\ NVIC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((NVIC\_Type\ \ \ \ \ \ *)\ \ \ \ \ NVIC\_BASE\ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01781\ \textcolor{preprocessor}{\#define\ ITM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((ITM\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ ITM\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01782\ \textcolor{preprocessor}{\#define\ DWT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((DWT\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ DWT\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01783\ \textcolor{preprocessor}{\#define\ TPI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((TPI\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ TPI\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01784\ \textcolor{preprocessor}{\#define\ CoreDebug\ \ \ \ \ \ \ \ \ \ \ ((CoreDebug\_Type\ *)\ \ \ \ \ CoreDebug\_BASE)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01785\ }
\DoxyCodeLine{01786\ \textcolor{preprocessor}{\#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{01787\ \textcolor{preprocessor}{\ \ \#define\ MPU\_BASE\ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0D90UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01788\ \textcolor{preprocessor}{\ \ \#define\ MPU\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((MPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ MPU\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01789\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01790\ }
\DoxyCodeLine{01791\ \textcolor{preprocessor}{\#define\ FPU\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0F30UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01792\ \textcolor{preprocessor}{\#define\ FPU\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((FPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ FPU\_BASE\ \ \ \ \ \ )\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01793\ }
\DoxyCodeLine{01795\ }
\DoxyCodeLine{01796\ }
\DoxyCodeLine{01797\ }
\DoxyCodeLine{01798\ \textcolor{comment}{/*******************************************************************************}}
\DoxyCodeLine{01799\ \textcolor{comment}{\ *\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Hardware\ Abstraction\ Layer}}
\DoxyCodeLine{01800\ \textcolor{comment}{\ \ Core\ Function\ Interface\ contains:}}
\DoxyCodeLine{01801\ \textcolor{comment}{\ \ -\/\ Core\ NVIC\ Functions}}
\DoxyCodeLine{01802\ \textcolor{comment}{\ \ -\/\ Core\ SysTick\ Functions}}
\DoxyCodeLine{01803\ \textcolor{comment}{\ \ -\/\ Core\ Debug\ Functions}}
\DoxyCodeLine{01804\ \textcolor{comment}{\ \ -\/\ Core\ Register\ Access\ Functions}}
\DoxyCodeLine{01805\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{01809\ }
\DoxyCodeLine{01810\ }
\DoxyCodeLine{01811\ }
\DoxyCodeLine{01812\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ NVIC\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{01819\ }
\DoxyCodeLine{01820\ \textcolor{preprocessor}{\#ifdef\ CMSIS\_NVIC\_VIRTUAL}}
\DoxyCodeLine{01821\ \textcolor{preprocessor}{\ \ \#ifndef\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{01822\ \textcolor{preprocessor}{\ \ \ \ \#define\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE\ "{}cmsis\_nvic\_virtual.h"{}}}
\DoxyCodeLine{01823\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{01824\ \textcolor{preprocessor}{\ \ \#include\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{01825\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{01826\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPriorityGrouping\ \ \ \ \_\_NVIC\_SetPriorityGrouping}}
\DoxyCodeLine{01827\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPriorityGrouping\ \ \ \ \_\_NVIC\_GetPriorityGrouping}}
\DoxyCodeLine{01828\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_EnableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_EnableIRQ}}
\DoxyCodeLine{01829\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetEnableIRQ\ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetEnableIRQ}}
\DoxyCodeLine{01830\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_DisableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_DisableIRQ}}
\DoxyCodeLine{01831\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPendingIRQ\ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetPendingIRQ}}
\DoxyCodeLine{01832\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPendingIRQ\ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetPendingIRQ}}
\DoxyCodeLine{01833\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_ClearPendingIRQ\ \ \ \ \ \ \ \ \_\_NVIC\_ClearPendingIRQ}}
\DoxyCodeLine{01834\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetActive\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetActive}}
\DoxyCodeLine{01835\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPriority\ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetPriority}}
\DoxyCodeLine{01836\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPriority\ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetPriority}}
\DoxyCodeLine{01837\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SystemReset\ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SystemReset}}
\DoxyCodeLine{01838\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ CMSIS\_NVIC\_VIRTUAL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01839\ }
\DoxyCodeLine{01840\ \textcolor{preprocessor}{\#ifdef\ CMSIS\_VECTAB\_VIRTUAL}}
\DoxyCodeLine{01841\ \textcolor{preprocessor}{\ \ \#ifndef\ CMSIS\_VECTAB\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{01842\ \textcolor{preprocessor}{\ \ \ \ \#define\ CMSIS\_VECTAB\_VIRTUAL\_HEADER\_FILE\ "{}cmsis\_vectab\_virtual.h"{}}}
\DoxyCodeLine{01843\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{01844\ \textcolor{preprocessor}{\ \ \#include\ CMSIS\_VECTAB\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{01845\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{01846\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetVector\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetVector}}
\DoxyCodeLine{01847\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetVector\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetVector}}
\DoxyCodeLine{01848\ \textcolor{preprocessor}{\#endif\ \ }\textcolor{comment}{/*\ (CMSIS\_VECTAB\_VIRTUAL)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01849\ }
\DoxyCodeLine{01850\ \textcolor{preprocessor}{\#define\ NVIC\_USER\_IRQ\_OFFSET\ \ \ \ \ \ \ \ \ \ 16}}
\DoxyCodeLine{01851\ }
\DoxyCodeLine{01852\ }
\DoxyCodeLine{01853\ \textcolor{comment}{/*\ The\ following\ EXC\_RETURN\ values\ are\ saved\ the\ LR\ on\ exception\ entry\ */}}
\DoxyCodeLine{01854\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_HANDLER\ \ \ \ \ \ \ \ \ (0xFFFFFFF1UL)\ \ \ \ \ }\textcolor{comment}{/*\ return\ to\ Handler\ mode,\ uses\ MSP\ after\ return\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01855\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_THREAD\_MSP\ \ \ \ \ \ (0xFFFFFFF9UL)\ \ \ \ \ }\textcolor{comment}{/*\ return\ to\ Thread\ mode,\ uses\ MSP\ after\ return\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01856\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_THREAD\_PSP\ \ \ \ \ \ (0xFFFFFFFDUL)\ \ \ \ \ }\textcolor{comment}{/*\ return\ to\ Thread\ mode,\ uses\ PSP\ after\ return\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01857\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_HANDLER\_FPU\ \ \ \ \ (0xFFFFFFE1UL)\ \ \ \ \ }\textcolor{comment}{/*\ return\ to\ Handler\ mode,\ uses\ MSP\ after\ return,\ restore\ floating-\/point\ state\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01858\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_THREAD\_MSP\_FPU\ \ (0xFFFFFFE9UL)\ \ \ \ \ }\textcolor{comment}{/*\ return\ to\ Thread\ mode,\ uses\ MSP\ after\ return,\ restore\ floating-\/point\ state\ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01859\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_THREAD\_PSP\_FPU\ \ (0xFFFFFFEDUL)\ \ \ \ \ }\textcolor{comment}{/*\ return\ to\ Thread\ mode,\ uses\ PSP\ after\ return,\ restore\ floating-\/point\ state\ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01860\ }
\DoxyCodeLine{01861\ }
\DoxyCodeLine{01871\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \_\_NVIC\_SetPriorityGrouping(uint32\_t\ PriorityGroup)}
\DoxyCodeLine{01872\ \{}
\DoxyCodeLine{01873\ \ \ uint32\_t\ reg\_value;}
\DoxyCodeLine{01874\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{01875\ }
\DoxyCodeLine{01876\ \ \ reg\_value\ \ =\ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ read\ old\ register\ configuration\ \ \ \ */}}
\DoxyCodeLine{01877\ \ \ reg\_value\ \&=\ \string~((uint32\_t)(\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga90c7cf0c490e7ae55f9503a7fda1dd22}{SCB\_AIRCR\_VECTKEY\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}}));\ \textcolor{comment}{/*\ clear\ bits\ to\ change\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{01878\ \ \ reg\_value\ \ =\ \ (reg\_value\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |}
\DoxyCodeLine{01879\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ |}
\DoxyCodeLine{01880\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (PriorityGroupTmp\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}})\ \ );\ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Insert\ write\ key\ and\ priority\ group\ */}}
\DoxyCodeLine{01881\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ =\ \ reg\_value;}
\DoxyCodeLine{01882\ \}}
\DoxyCodeLine{01883\ }
\DoxyCodeLine{01884\ }
\DoxyCodeLine{01890\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core_debug_gae1de06155d072758b3453edb07d12459}{\_\_NVIC\_GetPriorityGrouping}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{01891\ \{}
\DoxyCodeLine{01892\ \ \ \textcolor{keywordflow}{return}\ ((uint32\_t)((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ >>\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}}));}
\DoxyCodeLine{01893\ \}}
\DoxyCodeLine{01894\ }
\DoxyCodeLine{01895\ }
\DoxyCodeLine{01902\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga71227e1376cde11eda03fcb62f1b33ea}{\_\_NVIC\_EnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01903\ \{}
\DoxyCodeLine{01904\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01905\ \ \ \{}
\DoxyCodeLine{01906\ \ \ \ \ \_\_COMPILER\_BARRIER();}
\DoxyCodeLine{01907\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01908\ \ \ \ \ \_\_COMPILER\_BARRIER();}
\DoxyCodeLine{01909\ \ \ \}}
\DoxyCodeLine{01910\ \}}
\DoxyCodeLine{01911\ }
\DoxyCodeLine{01912\ }
\DoxyCodeLine{01921\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaaeb5e7cc0eaad4e2817272e7bf742083}{\_\_NVIC\_GetEnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01922\ \{}
\DoxyCodeLine{01923\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01924\ \ \ \{}
\DoxyCodeLine{01925\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{01926\ \ \ \}}
\DoxyCodeLine{01927\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01928\ \ \ \{}
\DoxyCodeLine{01929\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{01930\ \ \ \}}
\DoxyCodeLine{01931\ \}}
\DoxyCodeLine{01932\ }
\DoxyCodeLine{01933\ }
\DoxyCodeLine{01940\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gae016e4c1986312044ee768806537d52f}{\_\_NVIC\_DisableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01941\ \{}
\DoxyCodeLine{01942\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01943\ \ \ \{}
\DoxyCodeLine{01944\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01945\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{01946\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{01947\ \ \ \}}
\DoxyCodeLine{01948\ \}}
\DoxyCodeLine{01949\ }
\DoxyCodeLine{01950\ }
\DoxyCodeLine{01959\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga5a92ca5fa801ad7adb92be7257ab9694}{\_\_NVIC\_GetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01960\ \{}
\DoxyCodeLine{01961\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01962\ \ \ \{}
\DoxyCodeLine{01963\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{01964\ \ \ \}}
\DoxyCodeLine{01965\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01966\ \ \ \{}
\DoxyCodeLine{01967\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{01968\ \ \ \}}
\DoxyCodeLine{01969\ \}}
\DoxyCodeLine{01970\ }
\DoxyCodeLine{01971\ }
\DoxyCodeLine{01978\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaabefdd4b790b9a7308929938c0c1e1ad}{\_\_NVIC\_SetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01979\ \{}
\DoxyCodeLine{01980\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01981\ \ \ \{}
\DoxyCodeLine{01982\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01983\ \ \ \}}
\DoxyCodeLine{01984\ \}}
\DoxyCodeLine{01985\ }
\DoxyCodeLine{01986\ }
\DoxyCodeLine{01993\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga562a86dbdf14827d0fee8fdafb04d191}{\_\_NVIC\_ClearPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{01994\ \{}
\DoxyCodeLine{01995\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{01996\ \ \ \{}
\DoxyCodeLine{01997\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{01998\ \ \ \}}
\DoxyCodeLine{01999\ \}}
\DoxyCodeLine{02000\ }
\DoxyCodeLine{02001\ }
\DoxyCodeLine{02010\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaa2837003c28c45abf193fe5e8d27f593}{\_\_NVIC\_GetActive}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02011\ \{}
\DoxyCodeLine{02012\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02013\ \ \ \{}
\DoxyCodeLine{02014\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IABR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02015\ \ \ \}}
\DoxyCodeLine{02016\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02017\ \ \ \{}
\DoxyCodeLine{02018\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02019\ \ \ \}}
\DoxyCodeLine{02020\ \}}
\DoxyCodeLine{02021\ }
\DoxyCodeLine{02022\ }
\DoxyCodeLine{02032\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga505338e23563a9c074910fb14e7d45fd}{\_\_NVIC\_SetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ priority)}
\DoxyCodeLine{02033\ \{}
\DoxyCodeLine{02034\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02035\ \ \ \{}
\DoxyCodeLine{02036\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IP[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02037\ \ \ \}}
\DoxyCodeLine{02038\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02039\ \ \ \{}
\DoxyCodeLine{02040\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHPR[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02041\ \ \ \}}
\DoxyCodeLine{02042\ \}}
\DoxyCodeLine{02043\ }
\DoxyCodeLine{02044\ }
\DoxyCodeLine{02054\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaeb9dc99c8e7700668813144261b0bc73}{\_\_NVIC\_GetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02055\ \{}
\DoxyCodeLine{02056\ }
\DoxyCodeLine{02057\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02058\ \ \ \{}
\DoxyCodeLine{02059\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IP[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{02060\ \ \ \}}
\DoxyCodeLine{02061\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02062\ \ \ \{}
\DoxyCodeLine{02063\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHPR[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{02064\ \ \ \}}
\DoxyCodeLine{02065\ \}}
\DoxyCodeLine{02066\ }
\DoxyCodeLine{02067\ }
\DoxyCodeLine{02079\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gadb94ac5d892b376e4f3555ae0418ebac}{NVIC\_EncodePriority}}\ (uint32\_t\ PriorityGroup,\ uint32\_t\ PreemptPriority,\ uint32\_t\ SubPriority)}
\DoxyCodeLine{02080\ \{}
\DoxyCodeLine{02081\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02082\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{02083\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{02084\ }
\DoxyCodeLine{02085\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{02086\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{02087\ }
\DoxyCodeLine{02088\ \ \ \textcolor{keywordflow}{return}\ (}
\DoxyCodeLine{02089\ \ \ \ \ \ \ \ \ \ \ \ ((PreemptPriority\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL))\ <<\ SubPriorityBits)\ |}
\DoxyCodeLine{02090\ \ \ \ \ \ \ \ \ \ \ \ ((SubPriority\ \ \ \ \ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL)))}
\DoxyCodeLine{02091\ \ \ \ \ \ \ \ \ \ );}
\DoxyCodeLine{02092\ \}}
\DoxyCodeLine{02093\ }
\DoxyCodeLine{02094\ }
\DoxyCodeLine{02106\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga3387607fd8a1a32cccd77d2ac672dd96}{NVIC\_DecodePriority}}\ (uint32\_t\ Priority,\ uint32\_t\ PriorityGroup,\ uint32\_t*\ \textcolor{keyword}{const}\ pPreemptPriority,\ uint32\_t*\ \textcolor{keyword}{const}\ pSubPriority)}
\DoxyCodeLine{02107\ \{}
\DoxyCodeLine{02108\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02109\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{02110\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{02111\ }
\DoxyCodeLine{02112\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{02113\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{02114\ }
\DoxyCodeLine{02115\ \ \ *pPreemptPriority\ =\ (Priority\ >>\ SubPriorityBits)\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL);}
\DoxyCodeLine{02116\ \ \ *pSubPriority\ \ \ \ \ =\ (Priority\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ )\ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL);}
\DoxyCodeLine{02117\ \}}
\DoxyCodeLine{02118\ }
\DoxyCodeLine{02119\ }
\DoxyCodeLine{02129\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0df355460bc1783d58f9d72ee4884208}{\_\_NVIC\_SetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ vector)}
\DoxyCodeLine{02130\ \{}
\DoxyCodeLine{02131\ \ \ uint32\_t\ vectors\ =\ (uint32\_t\ )\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{02132\ \ \ (*\ (\textcolor{keywordtype}{int}\ *)\ (vectors\ +\ ((int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET)\ *\ 4))\ =\ vector;}
\DoxyCodeLine{02133\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02134\ \}}
\DoxyCodeLine{02135\ }
\DoxyCodeLine{02136\ }
\DoxyCodeLine{02145\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga44b665d2afb708121d9b10c76ff00ee5}{\_\_NVIC\_GetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02146\ \{}
\DoxyCodeLine{02147\ \ \ uint32\_t\ vectors\ =\ (uint32\_t\ )\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{02148\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(*\ (\textcolor{keywordtype}{int}\ *)\ (vectors\ +\ ((int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET)\ *\ 4));}
\DoxyCodeLine{02149\ \}}
\DoxyCodeLine{02150\ }
\DoxyCodeLine{02151\ }
\DoxyCodeLine{02156\ \_\_NO\_RETURN\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0d9aa2d30fa54b41eb780c16e35b676c}{\_\_NVIC\_SystemReset}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02157\ \{}
\DoxyCodeLine{02158\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ all\ outstanding\ memory\ accesses\ included}}
\DoxyCodeLine{02159\ \textcolor{comment}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ buffered\ write\ are\ completed\ before\ reset\ */}}
\DoxyCodeLine{02160\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \ =\ (uint32\_t)((0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ \ \ \ |}
\DoxyCodeLine{02161\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ |}
\DoxyCodeLine{02162\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaae1181119559a5bd36e62afa373fa720}{SCB\_AIRCR\_SYSRESETREQ\_Msk}}\ \ \ \ );\ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Keep\ priority\ group\ unchanged\ */}}
\DoxyCodeLine{02163\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ completion\ of\ memory\ access\ */}}
\DoxyCodeLine{02164\ }
\DoxyCodeLine{02165\ \ \ \textcolor{keywordflow}{for}(;;)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ wait\ until\ reset\ */}}
\DoxyCodeLine{02166\ \ \ \{}
\DoxyCodeLine{02167\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gabd585ddc865fb9b7f2493af1eee1a572}{\_\_NOP}}();}
\DoxyCodeLine{02168\ \ \ \}}
\DoxyCodeLine{02169\ \}}
\DoxyCodeLine{02170\ }
\DoxyCodeLine{02172\ }
\DoxyCodeLine{02173\ }
\DoxyCodeLine{02174\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ MPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02175\ }
\DoxyCodeLine{02176\ \textcolor{preprocessor}{\#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02177\ }
\DoxyCodeLine{02178\ \textcolor{preprocessor}{\#include\ "{}mpu\_armv7.h"{}}}
\DoxyCodeLine{02179\ }
\DoxyCodeLine{02180\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02181\ }
\DoxyCodeLine{02182\ }
\DoxyCodeLine{02183\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ FPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02190\ }
\DoxyCodeLine{02199\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga6bcad99ce80a0e7e4ddc6f2379081756}{SCB\_GetFPUType}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02200\ \{}
\DoxyCodeLine{02201\ \ \ uint32\_t\ mvfr0;}
\DoxyCodeLine{02202\ }
\DoxyCodeLine{02203\ \ \ mvfr0\ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>MVFR0;}
\DoxyCodeLine{02204\ \ \ \textcolor{keywordflow}{if}\ \ \ \ \ \ ((mvfr0\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95008f205c9d25e4ffebdbdc50d5ae44}{FPU\_MVFR0\_Single\_precision\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga3f2c8c6c759ffe70f548a165602ea901}{FPU\_MVFR0\_Double\_precision\_Msk}}))\ ==\ 0x220U)}
\DoxyCodeLine{02205\ \ \ \{}
\DoxyCodeLine{02206\ \ \ \ \ \textcolor{keywordflow}{return}\ 2U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Double\ +\ Single\ precision\ FPU\ */}}
\DoxyCodeLine{02207\ \ \ \}}
\DoxyCodeLine{02208\ \ \ \textcolor{keywordflow}{else}\ \textcolor{keywordflow}{if}\ ((mvfr0\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95008f205c9d25e4ffebdbdc50d5ae44}{FPU\_MVFR0\_Single\_precision\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga3f2c8c6c759ffe70f548a165602ea901}{FPU\_MVFR0\_Double\_precision\_Msk}}))\ ==\ 0x020U)}
\DoxyCodeLine{02209\ \ \ \{}
\DoxyCodeLine{02210\ \ \ \ \ \textcolor{keywordflow}{return}\ 1U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Single\ precision\ FPU\ */}}
\DoxyCodeLine{02211\ \ \ \}}
\DoxyCodeLine{02212\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02213\ \ \ \{}
\DoxyCodeLine{02214\ \ \ \ \ \textcolor{keywordflow}{return}\ 0U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ No\ FPU\ */}}
\DoxyCodeLine{02215\ \ \ \}}
\DoxyCodeLine{02216\ \}}
\DoxyCodeLine{02217\ }
\DoxyCodeLine{02219\ }
\DoxyCodeLine{02220\ }
\DoxyCodeLine{02221\ }
\DoxyCodeLine{02222\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ Cache\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02229\ }
\DoxyCodeLine{02230\ \textcolor{comment}{/*\ Cache\ Size\ ID\ Register\ Macros\ */}}
\DoxyCodeLine{02231\ \textcolor{preprocessor}{\#define\ CCSIDR\_WAYS(x)\ \ \ \ \ \ \ \ \ (((x)\ \&\ SCB\_CCSIDR\_ASSOCIATIVITY\_Msk)\ >>\ SCB\_CCSIDR\_ASSOCIATIVITY\_Pos)}}
\DoxyCodeLine{02232\ \textcolor{preprocessor}{\#define\ CCSIDR\_SETS(x)\ \ \ \ \ \ \ \ \ (((x)\ \&\ SCB\_CCSIDR\_NUMSETS\_Msk\ \ \ \ \ \ )\ >>\ SCB\_CCSIDR\_NUMSETS\_Pos\ \ \ \ \ \ )}}
\DoxyCodeLine{02233\ }
\DoxyCodeLine{02234\ \textcolor{preprocessor}{\#define\ \_\_SCB\_DCACHE\_LINE\_SIZE\ \ 32U\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02235\ \textcolor{preprocessor}{\#define\ \_\_SCB\_ICACHE\_LINE\_SIZE\ \ 32U\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02236\ }
\DoxyCodeLine{02241\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga980ffe52af778f2535ccc52f25f9a7de}{SCB\_EnableICache}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02242\ \{}
\DoxyCodeLine{02243\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_ICACHE\_PRESENT)\ \&\&\ (\_\_ICACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02244\ \ \ \ \ \textcolor{keywordflow}{if}\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaf2ff8f5957edac919e28b536aa6c0a59}{SCB\_CCR\_IC\_Msk}})\ \textcolor{keywordflow}{return};\ \ \textcolor{comment}{/*\ return\ if\ ICache\ is\ already\ enabled\ */}}
\DoxyCodeLine{02245\ }
\DoxyCodeLine{02246\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02247\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02248\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>ICIALLU\ =\ 0UL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ invalidate\ I-\/Cache\ */}}
\DoxyCodeLine{02249\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02250\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02251\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCR\ |=\ \ (uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaf2ff8f5957edac919e28b536aa6c0a59}{SCB\_CCR\_IC\_Msk}};\ \ \textcolor{comment}{/*\ enable\ I-\/Cache\ */}}
\DoxyCodeLine{02252\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02253\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02254\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02255\ \}}
\DoxyCodeLine{02256\ }
\DoxyCodeLine{02257\ }
\DoxyCodeLine{02262\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga56baa06298799dea5f207d4c12d9d4a6}{SCB\_DisableICache}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02263\ \{}
\DoxyCodeLine{02264\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_ICACHE\_PRESENT)\ \&\&\ (\_\_ICACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02265\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02266\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02267\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCR\ \&=\ \string~(uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaf2ff8f5957edac919e28b536aa6c0a59}{SCB\_CCR\_IC\_Msk}};\ \ \textcolor{comment}{/*\ disable\ I-\/Cache\ */}}
\DoxyCodeLine{02268\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>ICIALLU\ =\ 0UL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ invalidate\ I-\/Cache\ */}}
\DoxyCodeLine{02269\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02270\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02271\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02272\ \}}
\DoxyCodeLine{02273\ }
\DoxyCodeLine{02274\ }
\DoxyCodeLine{02279\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga62419cb7e6773e3d9236f14e458c1b05}{SCB\_InvalidateICache}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02280\ \{}
\DoxyCodeLine{02281\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_ICACHE\_PRESENT)\ \&\&\ (\_\_ICACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02282\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02283\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02284\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>ICIALLU\ =\ 0UL;}
\DoxyCodeLine{02285\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02286\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02287\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02288\ \}}
\DoxyCodeLine{02289\ }
\DoxyCodeLine{02290\ }
\DoxyCodeLine{02299\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_gaf6bed290ff6916337b0ce6c09131f699}{SCB\_InvalidateICache\_by\_Addr}}\ (\textcolor{keywordtype}{void}\ *addr,\ int32\_t\ isize)}
\DoxyCodeLine{02300\ \{}
\DoxyCodeLine{02301\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_ICACHE\_PRESENT)\ \&\&\ (\_\_ICACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02302\ \ \ \ \ \textcolor{keywordflow}{if}\ (\ isize\ >\ 0\ )\ \{}
\DoxyCodeLine{02303\ \ \ \ \ \ \ \ int32\_t\ op\_size\ =\ isize\ +\ (((uint32\_t)addr)\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_gadd99421e7a7d7121063ef94b49f97e90}{\_\_SCB\_ICACHE\_LINE\_SIZE}}\ -\/\ 1U));}
\DoxyCodeLine{02304\ \ \ \ \ \ \ uint32\_t\ op\_addr\ =\ (uint32\_t)addr\ \textcolor{comment}{/*\ \&\ \string~(\_\_SCB\_ICACHE\_LINE\_SIZE\ -\/\ 1U)\ */};}
\DoxyCodeLine{02305\ }
\DoxyCodeLine{02306\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02307\ }
\DoxyCodeLine{02308\ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02309\ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>ICIMVAU\ =\ op\_addr;\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ register\ accepts\ only\ 32byte\ aligned\ values,\ only\ bits\ 31..5\ are\ valid\ */}}
\DoxyCodeLine{02310\ \ \ \ \ \ \ \ \ op\_addr\ +=\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_gadd99421e7a7d7121063ef94b49f97e90}{\_\_SCB\_ICACHE\_LINE\_SIZE}};}
\DoxyCodeLine{02311\ \ \ \ \ \ \ \ \ op\_size\ -\/=\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_gadd99421e7a7d7121063ef94b49f97e90}{\_\_SCB\_ICACHE\_LINE\_SIZE}};}
\DoxyCodeLine{02312\ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}\ (\ op\_size\ >\ 0\ );}
\DoxyCodeLine{02313\ }
\DoxyCodeLine{02314\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02315\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02316\ \ \ \ \ \}}
\DoxyCodeLine{02317\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02318\ \}}
\DoxyCodeLine{02319\ }
\DoxyCodeLine{02320\ }
\DoxyCodeLine{02325\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga3861db932100ccb53f994e2cc68ed79c}{SCB\_EnableDCache}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02326\ \{}
\DoxyCodeLine{02327\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_DCACHE\_PRESENT)\ \&\&\ (\_\_DCACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02328\ \ \ \ \ uint32\_t\ ccsidr;}
\DoxyCodeLine{02329\ \ \ \ \ uint32\_t\ sets;}
\DoxyCodeLine{02330\ \ \ \ \ uint32\_t\ ways;}
\DoxyCodeLine{02331\ }
\DoxyCodeLine{02332\ \ \ \ \ \textcolor{keywordflow}{if}\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga57b3909dff40a9c28ec50991e4202678}{SCB\_CCR\_DC\_Msk}})\ \textcolor{keywordflow}{return};\ \ \textcolor{comment}{/*\ return\ if\ DCache\ is\ already\ enabled\ */}}
\DoxyCodeLine{02333\ }
\DoxyCodeLine{02334\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CSSELR\ =\ 0U;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ select\ Level\ 1\ data\ cache\ */}}
\DoxyCodeLine{02335\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02336\ }
\DoxyCodeLine{02337\ \ \ \ \ ccsidr\ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCSIDR;}
\DoxyCodeLine{02338\ }
\DoxyCodeLine{02339\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ invalidate\ D-\/Cache\ */}}
\DoxyCodeLine{02340\ \ \ \ \ sets\ =\ (uint32\_t)(CCSIDR\_SETS(ccsidr));}
\DoxyCodeLine{02341\ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02342\ \ \ \ \ \ \ ways\ =\ (uint32\_t)(CCSIDR\_WAYS(ccsidr));}
\DoxyCodeLine{02343\ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02344\ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>DCISW\ =\ (((sets\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaea6bd5b7d1c47c7db06afdecc6e49281}{SCB\_DCISW\_SET\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gab08fbef94f7d068a7c0217e074c697f9}{SCB\_DCISW\_SET\_Msk}})\ |}
\DoxyCodeLine{02345\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((ways\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaa6a2a5e1707c9ef277e67dacd4e247fd}{SCB\_DCISW\_WAY\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabfe6096a36807e0b7e1d09a06ef1d750}{SCB\_DCISW\_WAY\_Msk}})\ \ );}
\DoxyCodeLine{02346\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#if\ defined\ (\ \_\_CC\_ARM\ )}}
\DoxyCodeLine{02347\ \ \ \ \ \ \ \ \ \ \ \_\_schedule\_barrier();}
\DoxyCodeLine{02348\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#endif}}
\DoxyCodeLine{02349\ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}\ (ways-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02350\ \ \ \ \ \}\ \textcolor{keywordflow}{while}(sets-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02351\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02352\ }
\DoxyCodeLine{02353\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCR\ |=\ \ (uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga57b3909dff40a9c28ec50991e4202678}{SCB\_CCR\_DC\_Msk}};\ \ \textcolor{comment}{/*\ enable\ D-\/Cache\ */}}
\DoxyCodeLine{02354\ }
\DoxyCodeLine{02355\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02356\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02357\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02358\ \}}
\DoxyCodeLine{02359\ }
\DoxyCodeLine{02360\ }
\DoxyCodeLine{02365\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_gafe64b44d1a61483a947e44a77a9d3287}{SCB\_DisableDCache}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02366\ \{}
\DoxyCodeLine{02367\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_DCACHE\_PRESENT)\ \&\&\ (\_\_DCACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02368\ \ \ \ \ uint32\_t\ ccsidr;}
\DoxyCodeLine{02369\ \ \ \ \ uint32\_t\ sets;}
\DoxyCodeLine{02370\ \ \ \ \ uint32\_t\ ways;}
\DoxyCodeLine{02371\ }
\DoxyCodeLine{02372\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CSSELR\ =\ 0U;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ select\ Level\ 1\ data\ cache\ */}}
\DoxyCodeLine{02373\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02374\ }
\DoxyCodeLine{02375\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCR\ \&=\ \string~(uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga57b3909dff40a9c28ec50991e4202678}{SCB\_CCR\_DC\_Msk}};\ \ \textcolor{comment}{/*\ disable\ D-\/Cache\ */}}
\DoxyCodeLine{02376\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02377\ }
\DoxyCodeLine{02378\ \ \ \ \ ccsidr\ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCSIDR;}
\DoxyCodeLine{02379\ }
\DoxyCodeLine{02380\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ clean\ \&\ invalidate\ D-\/Cache\ */}}
\DoxyCodeLine{02381\ \ \ \ \ sets\ =\ (uint32\_t)(CCSIDR\_SETS(ccsidr));}
\DoxyCodeLine{02382\ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02383\ \ \ \ \ \ \ ways\ =\ (uint32\_t)(CCSIDR\_WAYS(ccsidr));}
\DoxyCodeLine{02384\ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02385\ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>DCCISW\ =\ (((sets\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga525f1bb9849e89b3eafbd53dcd51e296}{SCB\_DCCISW\_SET\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaf1b0bea5ab77d4ad7d5c21e77ca463ad}{SCB\_DCCISW\_SET\_Msk}})\ |}
\DoxyCodeLine{02386\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((ways\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaa90bd0b36679219d6a2144eba6eb96cd}{SCB\_DCCISW\_WAY\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaf2269bbe0bc7705e1da8f5ee0f581054}{SCB\_DCCISW\_WAY\_Msk}})\ \ );}
\DoxyCodeLine{02387\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#if\ defined\ (\ \_\_CC\_ARM\ )}}
\DoxyCodeLine{02388\ \ \ \ \ \ \ \ \ \ \ \_\_schedule\_barrier();}
\DoxyCodeLine{02389\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#endif}}
\DoxyCodeLine{02390\ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}\ (ways-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02391\ \ \ \ \ \}\ \textcolor{keywordflow}{while}(sets-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02392\ }
\DoxyCodeLine{02393\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02394\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02395\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02396\ \}}
\DoxyCodeLine{02397\ }
\DoxyCodeLine{02398\ }
\DoxyCodeLine{02403\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga99fe43c224644881935de135ceaa2dd9}{SCB\_InvalidateDCache}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02404\ \{}
\DoxyCodeLine{02405\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_DCACHE\_PRESENT)\ \&\&\ (\_\_DCACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02406\ \ \ \ \ uint32\_t\ ccsidr;}
\DoxyCodeLine{02407\ \ \ \ \ uint32\_t\ sets;}
\DoxyCodeLine{02408\ \ \ \ \ uint32\_t\ ways;}
\DoxyCodeLine{02409\ }
\DoxyCodeLine{02410\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CSSELR\ =\ 0U;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ select\ Level\ 1\ data\ cache\ */}}
\DoxyCodeLine{02411\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02412\ }
\DoxyCodeLine{02413\ \ \ \ \ ccsidr\ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCSIDR;}
\DoxyCodeLine{02414\ }
\DoxyCodeLine{02415\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ invalidate\ D-\/Cache\ */}}
\DoxyCodeLine{02416\ \ \ \ \ sets\ =\ (uint32\_t)(CCSIDR\_SETS(ccsidr));}
\DoxyCodeLine{02417\ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02418\ \ \ \ \ \ \ ways\ =\ (uint32\_t)(CCSIDR\_WAYS(ccsidr));}
\DoxyCodeLine{02419\ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02420\ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>DCISW\ =\ (((sets\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaea6bd5b7d1c47c7db06afdecc6e49281}{SCB\_DCISW\_SET\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gab08fbef94f7d068a7c0217e074c697f9}{SCB\_DCISW\_SET\_Msk}})\ |}
\DoxyCodeLine{02421\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((ways\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaa6a2a5e1707c9ef277e67dacd4e247fd}{SCB\_DCISW\_WAY\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabfe6096a36807e0b7e1d09a06ef1d750}{SCB\_DCISW\_WAY\_Msk}})\ \ );}
\DoxyCodeLine{02422\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#if\ defined\ (\ \_\_CC\_ARM\ )}}
\DoxyCodeLine{02423\ \ \ \ \ \ \ \ \ \ \ \_\_schedule\_barrier();}
\DoxyCodeLine{02424\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#endif}}
\DoxyCodeLine{02425\ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}\ (ways-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02426\ \ \ \ \ \}\ \textcolor{keywordflow}{while}(sets-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02427\ }
\DoxyCodeLine{02428\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02429\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02430\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02431\ \}}
\DoxyCodeLine{02432\ }
\DoxyCodeLine{02433\ }
\DoxyCodeLine{02438\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_gaf5585be5547cc60585d702a6129f4c17}{SCB\_CleanDCache}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02439\ \{}
\DoxyCodeLine{02440\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_DCACHE\_PRESENT)\ \&\&\ (\_\_DCACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02441\ \ \ \ \ uint32\_t\ ccsidr;}
\DoxyCodeLine{02442\ \ \ \ \ uint32\_t\ sets;}
\DoxyCodeLine{02443\ \ \ \ \ uint32\_t\ ways;}
\DoxyCodeLine{02444\ }
\DoxyCodeLine{02445\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CSSELR\ =\ 0U;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ select\ Level\ 1\ data\ cache\ */}}
\DoxyCodeLine{02446\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02447\ }
\DoxyCodeLine{02448\ \ \ \ \ ccsidr\ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCSIDR;}
\DoxyCodeLine{02449\ }
\DoxyCodeLine{02450\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ clean\ D-\/Cache\ */}}
\DoxyCodeLine{02451\ \ \ \ \ sets\ =\ (uint32\_t)(CCSIDR\_SETS(ccsidr));}
\DoxyCodeLine{02452\ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02453\ \ \ \ \ \ \ ways\ =\ (uint32\_t)(CCSIDR\_WAYS(ccsidr));}
\DoxyCodeLine{02454\ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02455\ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>DCCSW\ =\ (((sets\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae93985adc38a127bc8dc909ac58e8fea}{SCB\_DCCSW\_SET\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga669e16d98c8ea0e66afb04641971d98c}{SCB\_DCCSW\_SET\_Msk}})\ |}
\DoxyCodeLine{02456\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((ways\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga6cac2d69791e13af276d8306c796925f}{SCB\_DCCSW\_WAY\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8374e67655ac524284c9bb59eb2efa23}{SCB\_DCCSW\_WAY\_Msk}})\ \ );}
\DoxyCodeLine{02457\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#if\ defined\ (\ \_\_CC\_ARM\ )}}
\DoxyCodeLine{02458\ \ \ \ \ \ \ \ \ \ \ \_\_schedule\_barrier();}
\DoxyCodeLine{02459\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#endif}}
\DoxyCodeLine{02460\ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}\ (ways-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02461\ \ \ \ \ \}\ \textcolor{keywordflow}{while}(sets-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02462\ }
\DoxyCodeLine{02463\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02464\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02465\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02466\ \}}
\DoxyCodeLine{02467\ }
\DoxyCodeLine{02468\ }
\DoxyCodeLine{02473\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga5b22ca58709fadc326da83197a2f28bb}{SCB\_CleanInvalidateDCache}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02474\ \{}
\DoxyCodeLine{02475\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_DCACHE\_PRESENT)\ \&\&\ (\_\_DCACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02476\ \ \ \ \ uint32\_t\ ccsidr;}
\DoxyCodeLine{02477\ \ \ \ \ uint32\_t\ sets;}
\DoxyCodeLine{02478\ \ \ \ \ uint32\_t\ ways;}
\DoxyCodeLine{02479\ }
\DoxyCodeLine{02480\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CSSELR\ =\ 0U;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ select\ Level\ 1\ data\ cache\ */}}
\DoxyCodeLine{02481\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02482\ }
\DoxyCodeLine{02483\ \ \ \ \ ccsidr\ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>CCSIDR;}
\DoxyCodeLine{02484\ }
\DoxyCodeLine{02485\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ clean\ \&\ invalidate\ D-\/Cache\ */}}
\DoxyCodeLine{02486\ \ \ \ \ sets\ =\ (uint32\_t)(CCSIDR\_SETS(ccsidr));}
\DoxyCodeLine{02487\ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02488\ \ \ \ \ \ \ ways\ =\ (uint32\_t)(CCSIDR\_WAYS(ccsidr));}
\DoxyCodeLine{02489\ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02490\ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>DCCISW\ =\ (((sets\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga525f1bb9849e89b3eafbd53dcd51e296}{SCB\_DCCISW\_SET\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaf1b0bea5ab77d4ad7d5c21e77ca463ad}{SCB\_DCCISW\_SET\_Msk}})\ |}
\DoxyCodeLine{02491\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((ways\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaa90bd0b36679219d6a2144eba6eb96cd}{SCB\_DCCISW\_WAY\_Pos}})\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaf2269bbe0bc7705e1da8f5ee0f581054}{SCB\_DCCISW\_WAY\_Msk}})\ \ );}
\DoxyCodeLine{02492\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#if\ defined\ (\ \_\_CC\_ARM\ )}}
\DoxyCodeLine{02493\ \ \ \ \ \ \ \ \ \ \ \_\_schedule\_barrier();}
\DoxyCodeLine{02494\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#endif}}
\DoxyCodeLine{02495\ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}\ (ways-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02496\ \ \ \ \ \}\ \textcolor{keywordflow}{while}(sets-\/-\/\ !=\ 0U);}
\DoxyCodeLine{02497\ }
\DoxyCodeLine{02498\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02499\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02500\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02501\ \}}
\DoxyCodeLine{02502\ }
\DoxyCodeLine{02503\ }
\DoxyCodeLine{02512\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga9945b206324ddbcd32818f1a4e49df83}{SCB\_InvalidateDCache\_by\_Addr}}\ (\textcolor{keywordtype}{void}\ *addr,\ int32\_t\ dsize)}
\DoxyCodeLine{02513\ \{}
\DoxyCodeLine{02514\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_DCACHE\_PRESENT)\ \&\&\ (\_\_DCACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02515\ \ \ \ \ \textcolor{keywordflow}{if}\ (\ dsize\ >\ 0\ )\ \{\ }
\DoxyCodeLine{02516\ \ \ \ \ \ \ \ int32\_t\ op\_size\ =\ dsize\ +\ (((uint32\_t)addr)\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga8f36551f2593cd3715d1e68e37f97f12}{\_\_SCB\_DCACHE\_LINE\_SIZE}}\ -\/\ 1U));}
\DoxyCodeLine{02517\ \ \ \ \ \ \ uint32\_t\ op\_addr\ =\ (uint32\_t)addr\ \textcolor{comment}{/*\ \&\ \string~(\_\_SCB\_DCACHE\_LINE\_SIZE\ -\/\ 1U)\ */};}
\DoxyCodeLine{02518\ \ \ \ \ }
\DoxyCodeLine{02519\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02520\ }
\DoxyCodeLine{02521\ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02522\ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>DCIMVAC\ =\ op\_addr;\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ register\ accepts\ only\ 32byte\ aligned\ values,\ only\ bits\ 31..5\ are\ valid\ */}}
\DoxyCodeLine{02523\ \ \ \ \ \ \ \ \ op\_addr\ +=\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga8f36551f2593cd3715d1e68e37f97f12}{\_\_SCB\_DCACHE\_LINE\_SIZE}};}
\DoxyCodeLine{02524\ \ \ \ \ \ \ \ \ op\_size\ -\/=\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga8f36551f2593cd3715d1e68e37f97f12}{\_\_SCB\_DCACHE\_LINE\_SIZE}};}
\DoxyCodeLine{02525\ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}\ (\ op\_size\ >\ 0\ );}
\DoxyCodeLine{02526\ }
\DoxyCodeLine{02527\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02528\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02529\ \ \ \ \ \}}
\DoxyCodeLine{02530\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02531\ \}}
\DoxyCodeLine{02532\ }
\DoxyCodeLine{02533\ }
\DoxyCodeLine{02542\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_gab86b0b49bac2b14b21cc1590009efac5}{SCB\_CleanDCache\_by\_Addr}}\ (uint32\_t\ *addr,\ int32\_t\ dsize)}
\DoxyCodeLine{02543\ \{}
\DoxyCodeLine{02544\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_DCACHE\_PRESENT)\ \&\&\ (\_\_DCACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02545\ \ \ \ \ \textcolor{keywordflow}{if}\ (\ dsize\ >\ 0\ )\ \{\ }
\DoxyCodeLine{02546\ \ \ \ \ \ \ \ int32\_t\ op\_size\ =\ dsize\ +\ (((uint32\_t)addr)\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga8f36551f2593cd3715d1e68e37f97f12}{\_\_SCB\_DCACHE\_LINE\_SIZE}}\ -\/\ 1U));}
\DoxyCodeLine{02547\ \ \ \ \ \ \ uint32\_t\ op\_addr\ =\ (uint32\_t)addr\ \textcolor{comment}{/*\ \&\ \string~(\_\_SCB\_DCACHE\_LINE\_SIZE\ -\/\ 1U)\ */};}
\DoxyCodeLine{02548\ \ \ \ \ }
\DoxyCodeLine{02549\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02550\ }
\DoxyCodeLine{02551\ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02552\ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>DCCMVAC\ =\ op\_addr;\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ register\ accepts\ only\ 32byte\ aligned\ values,\ only\ bits\ 31..5\ are\ valid\ */}}
\DoxyCodeLine{02553\ \ \ \ \ \ \ \ \ op\_addr\ +=\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga8f36551f2593cd3715d1e68e37f97f12}{\_\_SCB\_DCACHE\_LINE\_SIZE}};}
\DoxyCodeLine{02554\ \ \ \ \ \ \ \ \ op\_size\ -\/=\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga8f36551f2593cd3715d1e68e37f97f12}{\_\_SCB\_DCACHE\_LINE\_SIZE}};}
\DoxyCodeLine{02555\ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}\ (\ op\_size\ >\ 0\ );}
\DoxyCodeLine{02556\ }
\DoxyCodeLine{02557\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02558\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02559\ \ \ \ \ \}}
\DoxyCodeLine{02560\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02561\ \}}
\DoxyCodeLine{02562\ }
\DoxyCodeLine{02563\ }
\DoxyCodeLine{02572\ \_\_STATIC\_FORCEINLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga853737b61ec075250d5991748fdd0e83}{SCB\_CleanInvalidateDCache\_by\_Addr}}\ (uint32\_t\ *addr,\ int32\_t\ dsize)}
\DoxyCodeLine{02573\ \{}
\DoxyCodeLine{02574\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_DCACHE\_PRESENT)\ \&\&\ (\_\_DCACHE\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{02575\ \ \ \ \ \textcolor{keywordflow}{if}\ (\ dsize\ >\ 0\ )\ \{\ }
\DoxyCodeLine{02576\ \ \ \ \ \ \ \ int32\_t\ op\_size\ =\ dsize\ +\ (((uint32\_t)addr)\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga8f36551f2593cd3715d1e68e37f97f12}{\_\_SCB\_DCACHE\_LINE\_SIZE}}\ -\/\ 1U));}
\DoxyCodeLine{02577\ \ \ \ \ \ \ uint32\_t\ op\_addr\ =\ (uint32\_t)addr\ \textcolor{comment}{/*\ \&\ \string~(\_\_SCB\_DCACHE\_LINE\_SIZE\ -\/\ 1U)\ */};}
\DoxyCodeLine{02578\ \ \ \ \ }
\DoxyCodeLine{02579\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02580\ }
\DoxyCodeLine{02581\ \ \ \ \ \ \ \textcolor{keywordflow}{do}\ \{}
\DoxyCodeLine{02582\ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>DCCIMVAC\ =\ op\_addr;\ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ register\ accepts\ only\ 32byte\ aligned\ values,\ only\ bits\ 31..5\ are\ valid\ */}}
\DoxyCodeLine{02583\ \ \ \ \ \ \ \ \ op\_addr\ +=\ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga8f36551f2593cd3715d1e68e37f97f12}{\_\_SCB\_DCACHE\_LINE\_SIZE}};}
\DoxyCodeLine{02584\ \ \ \ \ \ \ \ \ op\_size\ -\/=\ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___cache_functions_ga8f36551f2593cd3715d1e68e37f97f12}{\_\_SCB\_DCACHE\_LINE\_SIZE}};}
\DoxyCodeLine{02585\ \ \ \ \ \ \ \}\ \textcolor{keywordflow}{while}\ (\ op\_size\ >\ 0\ );}
\DoxyCodeLine{02586\ }
\DoxyCodeLine{02587\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02588\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02589\ \ \ \ \ \}}
\DoxyCodeLine{02590\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02591\ \}}
\DoxyCodeLine{02592\ }
\DoxyCodeLine{02594\ }
\DoxyCodeLine{02595\ }
\DoxyCodeLine{02596\ }
\DoxyCodeLine{02597\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ \ SysTick\ function\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02604\ }
\DoxyCodeLine{02605\ \textcolor{preprocessor}{\#if\ defined\ (\_\_Vendor\_SysTickConfig)\ \&\&\ (\_\_Vendor\_SysTickConfig\ ==\ 0U)}}
\DoxyCodeLine{02606\ }
\DoxyCodeLine{02618\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gae4e8f0238527c69f522029b93c8e5b78}{SysTick\_Config}}(uint32\_t\ ticks)}
\DoxyCodeLine{02619\ \{}
\DoxyCodeLine{02620\ \ \ \textcolor{keywordflow}{if}\ ((ticks\ -\/\ 1UL)\ >\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga265912a7962f0e1abd170336e579b1b1}{SysTick\_LOAD\_RELOAD\_Msk}})}
\DoxyCodeLine{02621\ \ \ \{}
\DoxyCodeLine{02622\ \ \ \ \ \textcolor{keywordflow}{return}\ (1UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Reload\ value\ impossible\ */}}
\DoxyCodeLine{02623\ \ \ \}}
\DoxyCodeLine{02624\ }
\DoxyCodeLine{02625\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gacd96c53beeaff8f603fcda425eb295de}{SysTick}}-\/>LOAD\ \ =\ (uint32\_t)(ticks\ -\/\ 1UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ set\ reload\ register\ */}}
\DoxyCodeLine{02626\ \ \ NVIC\_SetPriority\ (\mbox{\hyperlink{group___peripheral__interrupt__number__definition_gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7}{SysTick\_IRQn}},\ (1UL\ <<\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ -\/\ 1UL);\ \textcolor{comment}{/*\ set\ Priority\ for\ Systick\ Interrupt\ */}}
\DoxyCodeLine{02627\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gacd96c53beeaff8f603fcda425eb295de}{SysTick}}-\/>VAL\ \ \ =\ 0UL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Load\ the\ SysTick\ Counter\ Value\ */}}
\DoxyCodeLine{02628\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gacd96c53beeaff8f603fcda425eb295de}{SysTick}}-\/>CTRL\ \ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaa41d06039797423a46596bd313d57373}{SysTick\_CTRL\_CLKSOURCE\_Msk}}\ |}
\DoxyCodeLine{02629\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95bb984266ca764024836a870238a027}{SysTick\_CTRL\_TICKINT\_Msk}}\ \ \ |}
\DoxyCodeLine{02630\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga16c9fee0ed0235524bdeb38af328fd1f}{SysTick\_CTRL\_ENABLE\_Msk}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Enable\ SysTick\ IRQ\ and\ SysTick\ Timer\ */}}
\DoxyCodeLine{02631\ \ \ \textcolor{keywordflow}{return}\ (0UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Function\ successful\ */}}
\DoxyCodeLine{02632\ \}}
\DoxyCodeLine{02633\ }
\DoxyCodeLine{02634\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02635\ }
\DoxyCodeLine{02637\ }
\DoxyCodeLine{02638\ }
\DoxyCodeLine{02639\ }
\DoxyCodeLine{02640\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ Debug\ In/Output\ function\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02647\ }
\DoxyCodeLine{02648\ \textcolor{keyword}{extern}\ \textcolor{keyword}{volatile}\ int32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}};\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{02649\ \textcolor{preprocessor}{\#define\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ITM\_RXBUFFER\_EMPTY\ \ ((int32\_t)0x5AA55AA5U)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02650\ }
\DoxyCodeLine{02651\ }
\DoxyCodeLine{02660\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac90a497bd64286b84552c2c553d3419e}{ITM\_SendChar}}\ (uint32\_t\ ch)}
\DoxyCodeLine{02661\ \{}
\DoxyCodeLine{02662\ \ \ \textcolor{keywordflow}{if}\ (((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabae7cdf882def602cb787bb039ff6a43}{ITM}}-\/>TCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga7dd53e3bff24ac09d94e61cb595cb2d9}{ITM\_TCR\_ITMENA\_Msk}})\ !=\ 0UL)\ \&\&\ \ \ \ \ \ \textcolor{comment}{/*\ ITM\ enabled\ */}}
\DoxyCodeLine{02663\ \ \ \ \ \ \ ((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabae7cdf882def602cb787bb039ff6a43}{ITM}}-\/>TER\ \&\ 1UL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ )\ !=\ 0UL)\ \ \ )\ \ \ \ \ \textcolor{comment}{/*\ ITM\ Port\ \#0\ enabled\ */}}
\DoxyCodeLine{02664\ \ \ \{}
\DoxyCodeLine{02665\ \ \ \ \ \textcolor{keywordflow}{while}\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabae7cdf882def602cb787bb039ff6a43}{ITM}}-\/>PORT[0U].u32\ ==\ 0UL)}
\DoxyCodeLine{02666\ \ \ \ \ \{}
\DoxyCodeLine{02667\ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gabd585ddc865fb9b7f2493af1eee1a572}{\_\_NOP}}();}
\DoxyCodeLine{02668\ \ \ \ \ \}}
\DoxyCodeLine{02669\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabae7cdf882def602cb787bb039ff6a43}{ITM}}-\/>PORT[0U].u8\ =\ (uint8\_t)ch;}
\DoxyCodeLine{02670\ \ \ \}}
\DoxyCodeLine{02671\ \ \ \textcolor{keywordflow}{return}\ (ch);}
\DoxyCodeLine{02672\ \}}
\DoxyCodeLine{02673\ }
\DoxyCodeLine{02674\ }
\DoxyCodeLine{02681\ \_\_STATIC\_INLINE\ int32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gac3ee2c30a1ac4ed34c8a866a17decd53}{ITM\_ReceiveChar}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02682\ \{}
\DoxyCodeLine{02683\ \ \ int32\_t\ ch\ =\ -\/1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ no\ character\ available\ */}}
\DoxyCodeLine{02684\ }
\DoxyCodeLine{02685\ \ \ \textcolor{keywordflow}{if}\ (\mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}}\ !=\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa822cb398ee022b59e9e6c5d7bbb228a}{ITM\_RXBUFFER\_EMPTY}})}
\DoxyCodeLine{02686\ \ \ \{}
\DoxyCodeLine{02687\ \ \ \ \ ch\ =\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}};}
\DoxyCodeLine{02688\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}}\ =\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa822cb398ee022b59e9e6c5d7bbb228a}{ITM\_RXBUFFER\_EMPTY}};\ \ \ \ \ \ \ \textcolor{comment}{/*\ ready\ for\ next\ character\ */}}
\DoxyCodeLine{02689\ \ \ \}}
\DoxyCodeLine{02690\ }
\DoxyCodeLine{02691\ \ \ \textcolor{keywordflow}{return}\ (ch);}
\DoxyCodeLine{02692\ \}}
\DoxyCodeLine{02693\ }
\DoxyCodeLine{02694\ }
\DoxyCodeLine{02701\ \_\_STATIC\_INLINE\ int32\_t\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gae61ce9ca5917735325cd93b0fb21dd29}{ITM\_CheckChar}}\ (\textcolor{keywordtype}{void})}
\DoxyCodeLine{02702\ \{}
\DoxyCodeLine{02703\ }
\DoxyCodeLine{02704\ \ \ \textcolor{keywordflow}{if}\ (\mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_ga12e68e55a7badc271b948d6c7230b2a8}{ITM\_RxBuffer}}\ ==\ \mbox{\hyperlink{group___c_m_s_i_s__core___debug_functions_gaa822cb398ee022b59e9e6c5d7bbb228a}{ITM\_RXBUFFER\_EMPTY}})}
\DoxyCodeLine{02705\ \ \ \{}
\DoxyCodeLine{02706\ \ \ \ \ \textcolor{keywordflow}{return}\ (0);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ no\ character\ available\ */}}
\DoxyCodeLine{02707\ \ \ \}}
\DoxyCodeLine{02708\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02709\ \ \ \{}
\DoxyCodeLine{02710\ \ \ \ \ \textcolor{keywordflow}{return}\ (1);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ \ \ \ character\ available\ */}}
\DoxyCodeLine{02711\ \ \ \}}
\DoxyCodeLine{02712\ \}}
\DoxyCodeLine{02713\ }
\DoxyCodeLine{02715\ }
\DoxyCodeLine{02716\ }
\DoxyCodeLine{02717\ }
\DoxyCodeLine{02718\ }
\DoxyCodeLine{02719\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{02720\ \}}
\DoxyCodeLine{02721\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02722\ }
\DoxyCodeLine{02723\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_CORE\_CM7\_H\_DEPENDANT\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02724\ }
\DoxyCodeLine{02725\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_CMSIS\_GENERIC\ */}\textcolor{preprocessor}{}}

\end{DoxyCode}
